AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 250

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

If the second slave address in the Block Read Com-
mand is not the one of the Am79C975 controller, the
device will release the MDATA line to generate a NACK.
Key:
Detailed Functions
Global Enable/Disable
Bit 15 (SMIUEN) in BCR2 is used to enable/disable the
Serial Management Interface Unit in the Am79C975
controller. If SMIUEN is set to 0 (default), the SMIU is
disabled. If SMIUEN is set to 1, the SMIU is enabled.
BCR2 is programmable via the EEPROM.
Identification
The SMIU of the Am79C975 controller provides a com-
prehensive set of registers that allow the identification
of the device. ID information includes Vendor ID, De-
vice ID and Revision ID. In addition, the Subsystem
Vendor ID and Subsystem ID allow a system manufac-
turer to differentiate his product from a product by an-
other vendor who is also using the Am79C975
controller. All SMIU ID registers are shadow registers
of the respective PCI registers and can be initialized via
the EEPROM (with the exception of the Revision ID).
The host can verify that the registers are correctly ini-
tialized from the EEPROM by checking the PVALID bit
in the SMIU Am79C975 Status register.
Initialization
The SMIU of the Am79C975 controller does not require
any complex initialization in order to transmit or receive
management frames. Only the acknowledgment frame
filter needs to be setup in order to receive incoming
frames (see section Receive Operation later).
The host should check the content of the Transceiver
Status register to make sure the Am79C975 controller
is connected to a network (LINK set to 1), before any
transmit or receive operation is started.
250
S
1
Master to Am79C975 controller
Am79C975 controller to Master
Byte Count N
Slave Address
8
7
1
A
W
1
A
1
Figure 75. Block Read Command
P R E L I M I N A R Y
Data Byte 1
Am79C973/Am79C975
MReg Address
8
8
The master, receiving the NACK, must abort the cycle
by generating a STOP condition.
Note that the SMIU is not accessible while the
Am79C975 controller is reading the content of the EE-
PROM after H_RESET (for ~ 1.7 ms). The device will
not drive the Acknowledge bit during that time and the
access by the master will time-out.
SMIU Bus Frequency
The SMIU operating frequency is set by programming
BCR2 register bits. The equation for SMIU bus fre-
quency is F
a 25 MHz crystal has been used. The maximum value
of M is F (Hex) and N is 7 (Hex). With different combi-
nations of M and N, the SMIU bus frequency can vary
from 0.5 kHz to 1.25 MHz. It should be noted that the
frequencies that can be programmed through BCR2
are not continuous. For example, say F
then (M+1)*2
and N combinations that make an exact 250. With
M = E (Hex) and N = 3 (Hex), we get F
which will work with a 10 kHz bus frequency. The fol-
lowing is a list of BCR2 contents for various SMIU bus
frequencies.
A
1
BCR2 (Hex)
….
A643
A463
A642
A422
A641
A461
A202
A640
A460
I2C
A
1
N+1
= 2500/(M+1)*2
1
S
= 250. It is impossible to have such M
Data Byte N
Slave Address
8
N+1
7
kHz, assuming that
F
I2C
100
10
13
20
30
40
50
60
80
(kHz)
I2C
I2C
= 10 kHz,
= 10.41,
N
R
1
1
P
1
A
1