K9F1208D0B-D Samsung semiconductor, K9F1208D0B-D Datasheet
K9F1208D0B-D
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K9F1208D0B-D Summary of contents
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... K9F1208Q0B K9F1208D0B K9F1208U0B Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. Note : For more detailed features and specifications including FAQ, please refer to Samsung’ s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B 64M x 8 Bit NAND Flash Memory PRODUCT LIST Part Number K9F1208Q0B-D,H K9F1208D0B-Y,P K9F1208D0B-D,H K9F1208U0B-Y,P K9F1208U0B-D,H K9F1208U0B-V,F FEATURES Voltage Supply - 1.8V device(K9F1208Q0B) : 1.70~1.95V - 2.65V device(K9F1208D0B) : 2.4~2.9V - 3.3V device(K9F1208U0B) : 2.7 ~ 3.6 V Organization - Memory Cell Array : (64M + 2048K)bit x 8 bit - Data Register : (512 + 16)bit x 8bit Automatic Program and Erase ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B PIN CONFIGURATION (TSOP1) N.C N.C N.C N.C N.C N.C R N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8 0.45~0.75 0.018~0.030 K9F1208U0B-YCB0,PCB0/YIB0,PIB0 ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B PIN CONFIGURATION (FBGA K9F1208X0B-DCB0,HCB0/DIB0,HIB0 N.C N.C N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE I/ Vcc NC I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C Top View 4 Advance FLASH MEMORY N ...
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Package Dimensions 63-Ball FBGA (measured in millimeters) Top View 8.50 0.10 #A1 0.10MAX Bottom View 8.50 0. 7.20 0. 4.00 0. (Datum (Datum ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1208U0B-VCB0,FCB0/VIB0,FIB0 ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B PIN DESCRIPTION Pin Name I/O ~ I/O DATA INPUTS/OUTPUTS 0 7 (K9F1208X0B) The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Figure 1-1. K9F1208X0B FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F1208X0B ARRAY ORGANIZATION 128K Pages 1st half Page Register ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Product Introduction The K9F1208X0B is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Memory Map The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks ...
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... Supply Voltage Symbol 1.8V DEVICE V -0 2.45 IN/OUT 2.45 CCQ T BIAS T STG Ios +0.3V which, during transitions, may overshoot K9F1208X0B-XIB0 A K9F1208D0B(2.65V) Typ. Max Min Typ. 1.8 1.95 2.4 2.65 1.8 1.95 2.4 2. Advance FLASH MEMORY Rating 3.3V/2.65V DEVICE -0 4.6 -0 4.6 -0 4.6 -10 to +125 -40 to +125 ...
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... OH K9F1208U0B :I K9F1208Q0B :I Output Low Voltage Level V K9F1208D0B :I OL K9F1208U0B :I K9F1208Q0B :V Output Low Current(R/B) I (R/B) K9F1208D0B :V OL K9F1208U0B :V NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations less. (Recommended operating conditions otherwise noted.) Test Conditions 1.8V Min Typ =0mA ...
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... Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. AC TEST CONDITION (K9F1208X0B-XCB0 :TA K9F1208X0B-XIB0:TA=- K9F1208Q0B : Vcc=1.70V~1.95V , K9F1208D0B : Vcc=2.4V~2.9V , K9F1208U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels K9F1208Q0B:Output Load (Vcc :1 ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B PROGRAM / ERASE CHARACTERISTICS Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT Parameter Symbol CLE setup Time t CLS CLE Hold Time ...
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... NOTE reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us break the sequential read cycle, CE must be held high for longer time than tCEH. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin. Min K9F1208Q0B K9F1208D0B K9F1208U0B K9F1208Q0B K9F1208D0B K9F1208U0B ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B NAND Flash Technical Notes Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Pointer Operation of K9F1208X0B(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Device K9F1208X0B(X8 device) Command Latch Cycle CLE CE WE ALE I/O X Address Latch Cycle t CLS CLE ALS ALE I/O X I/O I/ CLH CLS ALS ALH Command ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Input Data Latch Cycle CLE CE t ALS ALE I/Ox Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE= ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Status Read Cycle CLE I/O X READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address 00h or 01h I Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h t CLR ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address Page(Row) Address Busy t WB ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Sequential Row Read Operation CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE 80h I Sequential Data Column Input Command Address R/B (Within a Block) Dout Ready Busy ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B BLOCK ERASE OPERATION CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command (ERASE ONE BLOCK DOh Erase Command 26 Advance FLASH MEMORY t BERS 70h I/O 0 Busy I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B FLASH MEMORY 27 Advance ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Multi-Plane Block Erase Operation CLE ALE RE I/O 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation ...
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... Byte Device Code Must be don’ t -cared 3 rd Byte th Supports Multi Plane Operation 4 Byte t REA 00h ECh Address. 1cycle Maker Code 29 Advance FLASH MEMORY Device C0h A5h Code Multi Plane Code Device Device Code K9F1208Q0B 36h K9F1208D0B 76h K9F1208U0B 76h ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Copy-Back Program Operation CLE ALE RE 00h I Column Page(Row) Address Address R/B On K9F1208U0B-Y,P or K9F1208U0B-V,F CE must be held low during 8Ah Column Address Busy Copy-Back Data Input Command ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Figure 7. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on X8 device(K9F1208X0B). ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I & Figure 9. Sequential Row Read1 Operation R/B I/O X 00h Start Add.(4Cycle) 01h & 00h Command) 1st half array Block The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Figure 10. Sequential Row Read2 Operation R/B I/O Start Add.(4Cycle) X 50h & Don’ t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 bytes single page program cycle ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15. Figure 14. Multi-Plane Program & ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane Copy- Back programming of four pages. Partial activation of four planes is also permitted. ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B FLASH MEMORY 39 Advance ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... Read ID mode until further commands are issued to it. Figure 21 shows the operation sequence. Figure 21. Read ID Operation 1 CLE CE WE ALE RE I 90h Address. 1cycle t CEA WHR t REA ECh 00h Maker code Device K9F1208Q0B K9F1208D0B K9F1208U0B 41 Advance FLASH MEMORY Device A5h Code Device code Multi-Plane code Device Code 36h 76h 76h C0h ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance Rp(min, 1.8V part) = Rp(min, 2.65V part) = Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit Vcc = 1.8V Ibusy 1 ...
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... K9F1208Q0B K9F1208D0B K9F1208U0B Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 24 ...