MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 11

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

CD Port (CDSTi/CDi, CDSTo/CDo)
The CD port is a serial bidirectional port used only in DUAL port mode. It is a means by which the DNIC receives its
control information for things such as setting the bit rate, enabling internal loopback tests, sending status
information back to the system and transferring low speed signalling data to and from the line.
The CD port is composed of the C and D-Channels. The C-channel is used for transferring control and status
information between the DNIC and the system. The D-channel is used for sending and receiving signalling
information and lower speed data between the line and the system. In DN/DUAL mode the DNIC receives a C-
channel on CDSTi while transmitting a C-channel on CDSTo. Fifteen channel times later (halfway through the
frame) a D-channel is received on CDSTi while a D-channel is transmitted on CDSTo. This is shown in Figure 7.
The order of the C and D bytes in DUAL port mode can be reversed by the mode select pins. See Table 1 for a
listing of the byte orientations.
The D-channel exists only in DN mode and may be used for transferring low speed data or signalling information
over the line at 8, 16 or 64 kbit/s (by using the DINB feature). The information passes transparently through the
DNIC and is transmitted to or received from the line at the bit rate selected in the Control Register.
If the bit rate is 80 kbit/s, only D0 is transmitted and received. At 160 kbit/s, D0 and D1 are transmitted and
received. When the DINB bit is set in the Control Register the entire D-channel is transmitted and received in the
B1-channel timeslot.
The C-channel is used for transferring control and status information between the DNIC and the system. The
Control and Diagnostics Registers are accessed through the C-channel. They contain information to control the
DNIC and carry out the diagnostics as well as the HK bit to be transmitted on the line as described in Tables 4 and
5. Bits 0 and 1 of the C-channel select between the Control and Diagnostics Register. If these bits are 0, 0 then the
C-channel information is written to the Control Register (Table 4). If they are 0, 1 the C-
Diagnostics Register (Table 5).
Bit
0
1
2
3
4
5
Reg Sel-1
Reg Sel-1
Reg Sel-2
PSEN
DINB
bit 0
Name
DRR
BRS
2
2
Reg Sel-2
bit 1
Register Select-1. Must be set to ’0’ to select the Control Register.
Register Select-2. Must be set to ’0’ to select the Control Register.
Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset
to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic
"1", the Diagnostics Register will not be reset.
Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.
D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding
to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit
times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel
timeslot on the line providing a 64 kbit/s D-channel link.
Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and
deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler
are disabled.
DRR
bit 2
Zarlink Semiconductor Inc.
bit 3
BRS
MT9171/72
11
DINB
bit 4
Default Mode Selection (Refer to Table 4a)
Description
PSEN
bit 5
ATTACK
bit 6
c
hannel is written to the
TxHK
bit 7
Data Sheet