MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 21

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

AC Electrical Characteristics
† Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25
1 TCK/RCK Clock Period
2 TCK/RCK Clock Width
3 TCK/RCK Clock Transition
4 CLD to TCK Setup Time
5 CLD to TCK Hold Time
6 CLD Width Low
7 CLD Period
Note 1:
Note 2:
Time
RCK
TCK
CLD
TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D
and may be skewed with respect to TCK due to end-to-end delay.
At the slave end TCK is phase locked to RCK.
The rising edge of TCK will lead the rising edge of RCK by approximately 90
Characteristics
2.4V
0.4V
2.4V
0.4V
2.4V
0.4V
°
C, for design aid only: not guaranteed and not subject to production testing.
†
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
- Clock Timing - MOD Mode (Figure 18)
Sym.
t
t
t
t
CLDW
CLDS
CLDH
CLDP
t
t
t
CW
CP
CT
t
CLDS
Min.
t
Zarlink Semiconductor Inc.
CLDW
80 kbit/s
MT9171/72
t
CLDH
3.125
3.125
Typ.*
8
12.5
6.25
6.05
20
x
t
21
CP
Max.
o
.
t
Min.
CP
t
CP
160 kbit/s
3.125
2.925
Typ.*
8
6.25
1.56
1.56
t
20
x
CW
t
CP
t
CW
Max.
o
output
Units
ms
ms
ms
ms
ms
ms
ns
t
CT
t
CT
Data Sheet
C
Conditions
L
=40pF
Test