MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 16

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Applications
Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE,
respectively. L
match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are
provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias
the received line signal for the L
center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as
lightning strikes.
If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This
increases the correlation between the transmit and receive data which may cause loss of convergence in the echo
canceller and high bit error rates.
In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least on ”1” must be fed into the
DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence.
F0
L
+5 V
OUT
CD Port ST-BUS
DV Port ST-BUS
Master Clocks
Mode Select
Lines
SYNC HK0
0.33 µF
0.33 µF
OUT
{
{
{
is connected to the coupling transformer through a resistor R2 and capacitors C2 and C2’ to
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
D
1
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
V
Figure 12 - Frame Format - 160 kbit/s (Modes 0, 2, 3, 4, 6)
D
MT9171/72
Ref
Bias
0
B1
IN
0
input. A 2:1 coupling transformer is used to couple to the line with a secondary
OSC1
OSC2
B1
L
F0o
OUT
1
L
To Next DNIC
IN
B1
2
NC
B1
Zarlink Semiconductor Inc.
R2 = 390Ω
R1 = 47Ω
3
MT9171/72
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
Characteristics
DN Mode.
Clock Timing
B1
C2’ = 1.5 nF
4
B1
16
C2 = 22 nF
5
B1
6
C1 = 0.33 µF
B1
7
B2
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L
+5V
D1 = D2 = MUR405
D2
0
B2
1
2 : 1
B2
2
B2
3
IN
B2
1.0 µF
≈ V
4
For 80 kbit/s: C2’ = 3.3 nF
Line Feed
Voltage
Bias
B2
5
B2
6
Data Sheet
B2
7
68 Volts
(Typ)
2.5 Joules
0.02 Watt
SYNC