MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 13

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Notes:
1.
depending upon the status of bit-3.
2.
3.
The Diagnostics Register Reset bit (bit 2) of the Control Register determines the reset state of the Diagnostics
Register. If, on writing to the Control Register, this bit is set to logic “0”, the Diagnostics Register will be reset
coincident with the frame pulse. When this bit is logic “1”, the Diagnostics Register will not be reset. In order to use
the diagnostic features, the Diagnostics Register must be continuously written to. The output C-channel sends
status information from the Status Register to the system along with the received HK bit as shown in Table 6.
Bit
Register
4
5
6
7
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
Do not use L
Do not use DSTo to DSTi loopback in MOD/MAS mode.
Status
1-2
4-6
0
3
7
Reg Sel-1
bit 0
Not Used
PSWAP
OUT
Name
SYNC
FUN
DLO
CHQual
to L
Rx HK
Future
0
SYNC
Name
1
1
ID
IN
Reg Sel-2
1
loopback in DN/SLV mode.
bit 1
Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
Channel Quality - These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
Housekeeping - This bit is the received housekeeping (HK) bit from the far end.
Future Functionality. These bits return Logic 1 when read.
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
1
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials
are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain
their normal designations.
Disable Line Out. When set to ’1’, the signal on L
L
Must be set to ’0’ for normal operation.
OUT
CHQual
pin functions normally.
bit 2
Loopback
2
Table 5 - Diagnostic Register
Table 6 - Status Register
Zarlink Semiconductor Inc.
bit 3
MT9171/72
Rx HK
3
13
bit 4
FUN
4
Description
Future Functionality
Function
Default Mode Selection
PSWAP
(Refer to Table 4a)
bit 5
5
OUT
is set to V
6
bit 6
DLO
Bias
Not Used
ID
7
. When set to ’0’,
bit 7
Data Sheet