MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 14

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT9171/72
Data Sheet
In MOD mode, the CD port is no longer an ST-BUS but is a serial bit stream operating at the bit rate selected. It
continues to transfer the C-channel but the D-channel and the HK bit no longer exist. DUAL port operation must be
used in MOD mode. The C-channel is clocked in and out of the CD port by TCK and CLD with TCK defining the bits
and CLD the channel boundaries of the data stream as shown in Figure 8.
Line Port (L
, L
)
IN
OUT
The line interface is made up of L
and L
with L
driving the transmit signal onto the line and L
receiving the
OUT
IN
OUT
IN
composite transmit and receive signal from the line. The line code used in the DNIC is Biphase and is shown in
Figure 10. The scrambled NRZ data is differentially encoded meaning the previous differential encoded output is
XOR’d with the current data bit which produces the current output. This is then biphase encoded where transitions
occur midway through the bit cell with a negative going transition indicating a logic "0" and a positive going
transition indicating a logic "1".
There are some major reasons for using a biphase line code. The power density is concentrated in a spectral
region that minimizes dispersion and differential attenuation. This can shorten the line response and reduce the
intersymbol interference which are critical for adaptive echo cancellation. There are regular zero crossings halfway
through every bit cell or baud which allows simple clock extraction at the receiving end. There is no D.C. content in
the code so that phantom power feed may be applied to the line and simple transformer coupling may be used with
no effect on the data. It is bipolar, making data reception simple and providing a high signal to noise ratio. The
signal is then passed through a bandpass filter which conditions the signal for the line by limiting the spectral
content from 0.2f
to 1.6f
and on to a line driver where it is made available to be put onto the line biased at
Baud
Baud
V
. The resulting transmit signal will have a distributed spectrum with a peak at 3/4f
. The transmit signal
Bias
Baud
(L
) may be disabled by holding the L
DIS pin high or by writing DLO (bit 6) of the Diagnostics Register to
OUT
OUT
logic “1”. When disabled, L
is forced to the V
level. L
DIS has an internal pull-down to allow this pin to be
OUT
Bias
OUT
left not connected in applications where this function is not required. The receive signal is the above transmit signal
superimposed on the signal from the remote end and any reflections or delayed symbols of the near end signal.
The frame format of the transmit data on the line is shown in Figures 11 and 12 for the DN mode at 80 and 160
kbit/s. At 80 kbit/s a SYNC bit for frame recovery, one bit of the D-channel and the B1-channel are transmitted. At
160 kbit/s a SYNC bit, the HK bit, two bits of the D-channel and both B1 and B2 channels are transmitted.
If the DINB bit of the Control Register is set, the entire D-channel is transmitted during the B1-channel timeslot. In
MOD mode the SYNC, HK and D-channel bits are not transmitted or received but rather a continuous data stream
at 80 or 160 kbit/s is present. No frame recovery information is present on the line in MOD mode.
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Zarlink Semiconductor Inc.