MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 7

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The composite transmit and receive signal is received at L
Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides
first order antialiasing for the received signal. Internal, partial cancellation of the near end signal may be disabled by
holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension
applications. The Precan pin features an internal pull-down which allows this pin to be left unconnected in
applications where this function is not required. The resultant signal passes through a receive filter to bandlimit and
equalize it. At this point, the echo estimate from the echo canceller is subtracted from the precancelled received
signal. This difference signal is then input to the echo canceller as an error signal and also squared up by a
comparator and passed to the biphase receiver. Within the echo canceller, the sign of this error signal is
determined. Depending on the sign, the echo estimate is either incremented or decremented and this new estimate
is stored back in RAM.
The timebase in both SLV and MAS modes (generated internally in SLV mode and externally in MAS mode) is
phase-locked to the received data stream. This phase-locked clock operates the Biphase Decoder, Descrambler
and Deprescrambler in MAS mode and the entire chip in SLV mode. The Biphase Decoder decodes the received
encoded bit stream resulting in the original NRZ data which is passed onto the Descrambler and Deprescrambler
where the data is restored to its original content by performing the reverse polynomials. The SYNC bits are
CLD
TCK
CDi
CDo
F0
C4
CDSTo
CDSTi
F0o
C
C
6
6
C
C
0
0
C
C
1
1
C
C
7
7
C
C
Channel Time 0
2
2
3.9 µsec
C
C
3
3
C
C
C
C
4
4
0
0
C
C
5
5
62.5 µsec
C
C
6
6
C
C
1
1
C
C
7
7
Figure 7 - CD Port (Modes 2,6)
Figure 8 - CD Port (Modes 1,5)
C
C
Zarlink Semiconductor Inc.
2
2
MT9171/72
125 µsec
C
C
7
3
3
IN
D
D
. On entering the DNIC this signal passes through a
0
0
C
C
D
D
4
4
1
1
Channel Time 16
D
D
2
2
D
D
3
3
C
C
5
5
D
D
4
4
D
D
5
5
C
C
D
D
6
6
6
6
D
D
7
7
C
C
7
7
C
C
Data Sheet
0
0
C
C
C
C
1
1
0
0