MT9171AE1 ZARLINK [Zarlink Semiconductor Inc], MT9171AE1 Datasheet - Page 6

• Manufacturer Part Number: MT9171AE1
• Description: Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-
channel D0 (and D1 for 160 kbit/s), the HK bit of the C-channel (160 kbit/s only) and a SYNC bit are combined in a
serial format to be sent out on the line by the Transmit Interface (Figures 11, 12). The SYNC bit produces an
alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. It is
possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the
true SYNC. To decrease the probability of this happening the DNIC may be programmed to put the data through a
prescrambler that scrambles the data according to a predetermined polynomial with respect to the SYNC bit. This
greatly decreases the probability that the SYNC pattern can be reproduced by any data on the line. In order for the
echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for
the SLV and MAS modes. These algorithms are calculated in such a way as to provide orthogonality between the
near and far end data streams such that the correlation between the two signals is very low.
For any two DNICs on a link, one must be in SLV mode with the other in MAS mode. The scrambled data is
differentially encoded which serves to make the data on the line polarity-independent. It is then biphase encoded as
shown in Figure 10. See “Line Interface” section for more details on the encoding. Before leaving the DNIC the
differentially encoded biphase data is passed through a pulse-shaping bandpass transmit filter that filters out the
high and low frequency components and conditions the signal for transmission on the line.
DSTo
DSTo
DSTi
DSTi
F0o
F0o
C4
C4
F0
F0
D
D
D
D
Channel Time 0
0
0
0
0
D
D-Channel
D
D
D
1
1
1
1
Channel Time 0
D
D
D
D
2
2
2
2
D-Channel
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
D
D
D
D
6
6
6
6
D
D
D
D
7
7
7
7
C
C
C
C
Channel Time 1
0
0
0
0
C
C
C-Channel
C
C
1
1
1
1
Figure 6 - DV Port - 160 kbit/s (Modes 0,4)
Figure 5 - DV Port - 80 kbit/s (Modes 0,4)
Channel Time 1
C
C
C
C
2
2
2
2
C-Channel
C
C
C
C
3
3
3
3
11.7 µsec
15.6 µsec
C
C
C
C
4
4
4
4
Zarlink Semiconductor Inc.
C
C
C
C
5
5
5
5
MT9171/72
C
C
C
C
6
6
6
6
C
C
C
C
7
7
7
7
B
B
B
B
Channel Time 2
7
7
7
7
6
B1-Channel
B
B
B
B
6
6
6
6
Channel Time 2
B
B
B
B
B1-Channel
5
5
5
5
B
B
B
B
4
4
4
4
B
B
B
B
3
3
3
3
B
B
B
B
2
2
2
2
B
B
B
B
1
1
1
1
B
B
B
B
0
0
0
0
B
B
7
7
B
B
6
6
Channel Time 3
B
B
5
5
B2-Channel
B
B
4
4
B
B
3
3
B
B
2
2
B
B
1
1
B
B
0
0
Data Sheet
D
D
D
D
0
0
0
0