ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 102

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ST52F510FMB6

Manufacturer Part Number
ST52F510FMB6
Description
8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
ST52F510/F513/F514
Figure 15.6 Single Master Configuration
15.4.8 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit (SPIE) and the interrupt mask
bit (MSKSPI) in the INT_MASK Configuration
Register is set.
102/106
SPI End of Transfer Event
Master Mode Fault Event
5V
MOSI
SS
SCK
SCK
MOSI
Master
MCU
MCU
Slave
MISO
MISO
SS
Interrupt Event
MOSI
SCK
Slave
MCU
MISO
SS
MOSI
SCK
Slave
MCU
MODF
Event
SPIF
Flag
MISO
SS
Control
Enable
SPIE
Bit
MOSI
SCK
from
Wait
Slave
MCU
Exit
Yes
Yes
MISO
SS
from
Exit
Halt
No
No

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