ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 87

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Acknowledge may be enabled and disabled via
software.
The I
address can be selected via software.
The speed of the I
between Standard (0-100KHz) and Fast I
400KHz).
14.3.3 SDA/SCL Line Control.
Transmitter mode : the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode : the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I
Figure 14.2 I
SDA
SCL
2
C interface address and/or general call
SDA
SCL
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL REGISTER (I2C_CCR)
CLOCK CONTROL
STATUS REGISTER 1 (I2C_SR1)
STATUS REGISTER 2 (I2C_SR2)
CONTROL REGISTER (I2C_CR)
DATA CONTROL
2
C bus mode.
2
C (100-
When the I
pins must be configured as floating open-drain I/O.
The value of the external pull-up resistance used
depends on the application.
14.4 Functional Description
By default the I
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First, the interface frequency must be configured
using the related bits of the Configuration
Registers.
14.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
OWN ADDRESS REGISTER (OAR)
DATA SHIFT REGISTER
2
CONTROL LOGIC
DATA REGISTER
C cell is enabled, the SDA and SCL
COMPARATOR
INTERRUPT
2
C interface operates in Slave
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