ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 39

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

4.8.4 Option Bytes.
First Protected Page (PG_LOCK)
Option Byte 5 (05h)
Reset Value: 0000 0000 (00h)
Bit 7-0: LCK7-0 First Page write protected
In this register the address of first page to be
protected in writing is specified. The pages
following this one are protected up to the page
specified by the PG_UNLOCK Option Byte (not
included among the protected ones).
First Page not Protected (PG_UNLOCK)
Option Byte 6 (06h)
Reset Value: 0000 0000 (00h)
Bit 7-0: UNLCK7-0 First Page not write protected
In this register the address of first page not write
protected after the protected ones is specified. The
pages following this one aren’t protected.
UNLCK7 UNLCK6 UNLCK5 UNLCK4 UNLCK3 UNLCK2 UNLCK1 UNLCK0
LCK7
7
7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
0
0
4.8.5 Input Register.
IAP Status Register (IAP_SR)
Input Register 40 (028h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-2: Not Used
Bit 1: PRTCD Page Protected
Bit 0: ABRT Writing operation aborted
The ABRT and PRTCD bits are reset after the next
successful data writing in the Flash of EEPROM
memory.
7
-
0: The writing has been completed
1: The writing has been aborted because the
0: The writing has been completed
1: The writing has been aborted because an
page is protected.
interrupt or another unspecified cause
occurred.
-
-
-
ST52F510/F513/F514
-
-
PRTCD
39/106
ABRT
0