ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 71

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

12 PWM/TIMERS
12.1 Introduction
ST52F510/513/514 offers two on-chip PWM/Timer
peripherals. All ST52F510/513/514 PWM/Timers
have the same internal structure. The timer
consists of a 16-bit counter with a 16-bit
programmable Prescaler, giving a maximum count
of 2
Each timer has two different working modes, which
can be selected by setting the correspondent bit
TxMOD
Register: Timer Mode and PWM (Pulse Width
Modulation) Mode.
All the Timers have Autoreload Functions; in PWM
Mode the reload value can be set by the user.
Each timer output is available on the apposite
external pins configured in Alternate Function and
in one of the Output modes.
PWM/Timer 0 can also use external START/STOP
signals in order to perform Input capture and
Output compare, external RESET signal, and
external CLOCK to count external events: TSTRT,
TRES and TCLK pins. In addition, the START/
STOP and RESET signals have configurable
polarity (falling or rising edge).
Remark: To use TRES, TSTRT, TCLK external
signals the related pins must be configured in
Alternate Function and in one of Input modes.
For each timer, the contents of the 16-bit counter
are incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and it can be read
at any instant of the counting phase by accessing
the Input Registers PWMx_COUNT_IN_x; the
value is stored in two 8-bit registers (MSB and
LSB) for each PWM/Timer.
Figure 12.1 PWM/Timer Counter block diagram
32
TMRCLKx
(see Figure 12.1).
of
the
BIT 0
BIT 0
PWMx_CR1
BIT 1
BIT 1
BIT 2
BIT 2
Configuration
BIT 3
BIT 3
16-BIT COUNTER
16-BIT PRESCALER
17 - 1 MULTIPLEXER
BIT 4
BIT 4
PRESCOUT
BIT 5
BIT 5
The Input Registers couple PWMx_CAPTURE_x
store the counter value after the last Stop signal
(only Timer Mode). The counter value is not stored
after a Reset Signal.
The peripheral status can also be read from the
Input Registers (one for each Timer). These
registers
status, TxOUT signal and the counter overflow
flag. This last signal is set after the first EOC and it
is reset by a Timer RESET (internal or external).
12.2 Timer Mode
Timer Mode is selected writing 0 in the TxMOD bit.
Each Timer requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 12.1). Each of these signals
can be generated internally, and/or externally only
for Timer 0, by using TRES, TSTRT and TCLK
pins.
The Prescaler output (PRESCOUT) increments
the Counter value on the rising edge. PRESCOUT
is obtained from the internal clock signal (CLKM)
or, only for TIMER0, from the external signal
provided on the apposite pin.
Note: The external clock signal applied on the
TCLK pin must have a frequency that is at least two
times smaller than the internal master clock.
The prescaler output period can be selected by
setting the TxPRESC bits with one of the 17
division factors available. TMRCLK frequency is
divided by a factor equal to the power of two of the
prescaler values (up to 2
TxRES resets the content of the 16-bit counter to
zero. It is generated by writing 0 in the TxRES bit
of the PWMx_CR1 Configuration Register and/or it
can be driven by the TRES pin if configured (only
Timer0).
report
BIT 14
BIT 14
START/STOP,
BIT 15
BIT 15
16
ST52F510/F513/F514
).
PRESCx
TxSTRT
TxRES
SET/RESET
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