ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 90

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST52F510/F513/F514
Figure 14.3 Tranfer Sequencing
90/106
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master transmitter:
10-bit Master receiver:
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
S Address A
S Address A
S
S Header
S
S
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register.
EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV3-1: EVF=1, AF=1, BTF=1, SCL=0; AF is cleared by reading I2C_SR2. BTF is cleared
by releasing the lines (STOP=1,STOP=0) or by readyng I2C_SR1 and writing I2C_OUT register
(I2C_OUT=FFh).Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen
EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register.
EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1
EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IIN register.
EV8: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT registe
Header
Address
Address
A
EV1
EV1 EV3
Address A
A
A
A
S
r
Data1
EV9
EV6
EV6 EV8
Header
S
r
Data1
Address A
Data1
EV5
EV1
A
A
Data1
Header
EV2
Data1
EV1 EV3
A
A
Data2
EV3
EV6 EV8
EV7
A
A
A
Data2
EV8
Data1
Data2
EV6
EV2
A
Data1
Data2
Data1
EV2
A
.....
A
A
EV3
EV7
EV3
DataN
.....
A
A
A
EV8
EV8
DataN
.....
.....
.....
EV7
A
DataN
.....
.....
DataN
DataN
.....
EV2
A
DataN
DataN
DataN
EV2
P
NA
NA
A
EV4
P
EV3-1
EV7
EV3-1
A
A
A
EV4
EV8
EV8
P
EV7
P
P
EV4
P
P
EV4
P