ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 67

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

10.3.4
In this mode (CONT=1, SEQ=1) a continuous
conversion flow is entered by a start event on the
selected channel sequence. The CH2-0 bits
indicate the last channel of the sequence.
At the end of each conversion the relative Input
Registers are updated with the last conversion
results, while the former values are lost.
The conversion continues until a stop command is
executed by writing a ‘0’ in the apposite AD_CR
Configuration Register bit STR.
10.4 Power Down Mode
Before enabling any A/D operation modes, set the
Power On bit (POW) of the Configuration Register
AD_CR to ‘1’ and then start the A/D Converter by
setting the STR bit. It is suggested to execute the
pre-charging after the Power on to speed-up the
auto calibration process. Clearing the Power On bit
is useful when the A/D is not used, reducing the
total chip power consumption. This state is also the
reset configuration and it is forced by hardware
when the core is in HALT state (after a HALT
instruction execution).
10.5 A/D Converter Register Description
The following registers are related to the use of the
A/D Converter.
10.5.1 A/D Converter Configuration Registers.
A/D Converter Control Register 1 (AD_CR1)
Configuration Register 8 (08h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-5: CH2-CH0 Channel Number
Bit 4: SCK A/D speed mode
CH2
7
0: Slow mode (800 kHz)
1: Fast mode (1600 kHz)
The number specified identifies the number
of channels to be converted (Multiple
Channel mode) or the channel to be
converted (One Channel mode)
CH1
Multiple Channels Continuous Mode.
CH0
SCK
SEQ
POW
CONT
STR
0
Bit 3: SEQ One/Multiple Channel Mode
Bit 2: POW A/D Converter Power Down/Up
Bit 1: CONT Single/Continuous Mode
Bit 0: STR A/D Converter Start bit
A/D Converter Control Register 2 (AD_CR2)
Configuration Register 47 (02Fh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-5: not used
Bit 4: PRECH Pre-charging process on/off
Bit 3: REF Voltage Reference (VREF) source
Bit 2: RESOL 8/10 bits resolution
Bit 1: INT1 Overflow interrupt mask
Bit 0: INT0 End of Conversion interrupt mask
7
-
0: One Channel Mode
1: Multiple Channel Mode
0: Power down
1: Power up
0: Single Mode
1: Continuous Mode
0: A/D Converter stopped
1: A/D Converter started
0: Pre-charge on (default)
1: Pre-charge off
0: Internal from Vdd
1: External from VREF pin
0: 10 bits
1: 8 bits
0: interrupt disabled
1: interrupt enabled (if MSKAD=1)
0: interrupt disabled
1: interrupt enabled (if MSKAD=1)
-
-
PRECH
ST52F510/F513/F514
REF
RESOL
INT1
67/106
INT0
0