ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 50

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST52F510/F513/F514
7 I/O PORTS
7.1 Introduction
ST52F510/F513/F514
flexible individually programmable multi-functional
I/O lines. The ST52F510/F513/F514 supplies
devices with up to 3 Ports (named from A to C) with
up to 22 I/O lines.
Each pin can be used as a digital I/O or can be
connected with a peripheral (Alternate Function).
The I/O lines belonging to Port A and Port B can
also be used to generate Port Interrupts.
The I/O Port pins can be configured in the following
modes:
These
programming three Configuration Registers for
each Port. All the pins that belong to the same Port
can be configured separately by setting the
corresponding bits in the three registers (see
Register Description).
To avoid side effects, the Configuration Registers
register are latched only when the Direction
Register (PORT_x_DDR) is written. For this
reason this register must be always written when
modifying the pin configuration.
All the I/O digital pins are TTL compatible and have
a Schmitt Trigger. The output buffer can supply
high current sink (up to 8mA).
Figure 7.1 Digital Pin
50/106
D IG ITAL OU T
Input high impedance (reset state)
Input with pull-up
Output with pull-up
Output push-pull
Output with weak pull-up
Output open drain
Interrupt with pull-up
Interrupt without pull-up
EN ABLE
PULL U P
EN ABLE
DAT A
DAT A
OU T
IN
eight
modes
are
can
characterized
be
PA D
selected
PO RT A,C,D ,E
PIN
by
by
7.2 Input Mode
The pins configured as input can be read by
accessing the corresponding Port Input Register
by means of the LDRI instruction. The addresses
for Port A , B and C are respectively 0 (00h), 1
(01h), and 2 (02h).
When executing the LDRI instruction all the signals
connected to the input pins of the Port are read and
the logical value is copied in the specified Register
File location. If some pins are configured in output,
the port buffer contents, which are the last written
logical values in the output pins, are read.
7.3 Output Mode
The pins configured as output can be written by
accessing the corresponding Port Output Register
by means of the LDPR, LDPI and LDPE
instructions. The addresses for Port A , B and C
are respectively, 0 (00h), 1 (01h), and 2 (02h).
When executing the above mentioned instructions,
the Port buffer is written and the Port pin signals
are modified. If some pins are configured as input
or as interrupt, the values are ignored.
7.4 Interrupt Mode
The pins configured as Interrupt Mode can
generate a Port Interrupt request. Only Port A and
Port B pins can be configured in this mode.
An Interrupt vector is associated to each Port:
there are two Port Interrupts available but more
pins of the ports can act as source at the same
time.
The Configuration Registers switch the signals
deriving from interrupt pins to an OR gate that
generates the interrupt request signal. The signal
deriving from the pins can be read, allowing the
discrimination of the interrupt sources when more
than one pin can generate the interrupt signal.
The interrupt trigger can be configured either in the
rising or falling edge of the external signal.
Figure 7.2 Analog Pin