ST52F510FMB6 STMICROELECTRONICS [STMicroelectronics], ST52F510FMB6 Datasheet - Page 84

• Manufacturer Part Number: ST52F510FMB6
• Description: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST52F510/F513/F514
13.4 SCI Register Description
The following registers are related to the use of the
SCI peripheral.
13.4.1 SCI Configuration Registers.
SCI Control Register 1 (
Configuration Register 22 (016h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: RXFINT SCDR_RX buffer full interrupt mask
Bit 6: OVRINT Overrun interrupt mask
Bit 5: BRKINT Break interrupt mask
Bit 4: TXEMINT SCDR_TX buffer empty interrupt
Bit 3: TXENINT TX end interrupt mask
Bit 2: PAR/T8 Parity type selection or TX 9th bit
Bit 1-0: FRM Frame type selection
Note: the SCI interrupts are not enabled unless the
bit 3 (MSKSCI) of the Configuration Register 0
(INT_MASK) is enabled (set to 1).
84/106
RXFINT OVRINT BRKINT TXEMINT TXENINT PAR/T8
7
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: interrupt disabled
1: interrupt enabled
0: parity odd if enabled, else TX 9th bit=0
1: parity even if enabled, else TX 9th bit=1
00: 8 bit, no parity, 1 stop bit
01: 8 bit, no parity, 2 stop bit
10: 8 bit, parity, 1 stop bit
11: 9 bit, no parity, 1 stop bit
SCI_CR1
)
2
FRM
0
SCI Control Register 2 (
Configuration Register 23 (017h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-4: PRESC_H Baud Rate prescaler (bit 11:8)
Bit 3-2: not used
Bit 1: RXSTRT Reception enable
Bit 0: TXSTRT Transmission enable
SCI Control Register 3 (
Configuration Register 43 (02Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0: PRESC_L Baud Rate prescaler (bit 7:0)
7
7
0: RX disabled
1: RX enabled
0: TX disabled
1: TX enabled
These bits are the higher part of the
prescaler (see SCI_CR3 Configuration
Register) which determinates the baud rate
of the communication, according to Table
13.1 and Table 13.2, as explained in
Paragraph 13.3.
These bits are the lower part of the
prescaler (see SCI_CR2 Configuration
Register) which determinates the baud rate
of the communication, according to Table
13.1 and Table 13.2, as explained in
Paragraph 13.3.
PRESC_H
4
PRESC_L
SCI_CR2
SCI_CR3
-
)
)
2
RXSTRT TXSTRT
0
0