K9K1G08U0M-YIB0 Samsung semiconductor, K9K1G08U0M-YIB0 Datasheet
K9K1G08U0M-YIB0
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K9K1G08U0M-YIB0 Summary of contents
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue 0.1 1.[Page 31] device code (76h) --> device code (79h) 1.Powerup sequence is added 0.2 : Recovery time of minimum required before internal circuit gets ready for any command sequences V CC ...
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... Command/Address/Data Multiplexed I/O Port Hardware Data Protection - Program/Erase Lockout During Power Transitions Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years Command Register Operation Intelligent Copy-Back Operation Package : - K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 : 48 - Pin TSOP I ( 0.5 mm pitch) Simultaneous Four Page/Block Program/Erase Pin Configuration N.C 1 N ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Figure 1. Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE Figure 2. Array Organization 256K Pages 1st half Page Register (=8,192 Blocks) (=256 Bytes) ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Product Introduction The K9K1G08U0M is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen col- umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Memory Map The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Pin Description Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the activating path for address to the internal address registers ...
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... Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol BIAS T STG +0.3V which, during transitions, may overshoot K9K1G08U0M-YIB0 A Symbol Min V 2 (Recommended operating conditions otherwise noted.) Symbol Test Conditions I 1 tRC=50ns ...
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... Refer to the attached technical notes for an appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed valid block, does not require Error Correct i on. AC Test Condition (K9K1G08U0M-YCB0 :TA K9K1G08U0M-YIB0:TA=- VCC=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The i nfor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the ac tual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Pointer Operation of K9K1G08U0M Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle t CLS CLE ALS ALE I CLH CLS ALS ALH Command ALH ALH ALS ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 * Input Data Latch Cycle CLE CE t ALS ALE I Serial Access Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 1 DIN 0 (CLE=L, WE=H, ALE=L) ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 * Status Read Cycle CLE I Read1 Operation (Read One Page) CLE ALE RE 00h or 01h I Column Address R/B t CLR t CLS t CLH WHR 70h AR2 Dout N ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O ~ 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O ~ 50h R/B M Address AR2 Dout ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Sequential Row Read Operation ( Within a Block ) CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R/B Dout 25, ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 BLOCK ERASE OPERATION CLE ALE RE I/O ~ 60h Page(Row) Address R/B Auto Block Erase Setup Command (ERASE ONE BLOCK DOh 25 Busy Erase Command 20 FLASH MEMORY t BERS 70h I/O 0 I/O =0 Successful Erase 0 Read Status ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 FLASH MEMORY 21 ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 CLE ALE RE I/O ~ 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Read ID Operation CLE CE WE ALE RE I 90h Read ID Command ID Defintition Table 90 ID: Access command = 90H Value 1 st Byte ECh Byte 79h 3 rd Byte A5h C0h 4 th Byte t REA 00h ECh Maker Code Device Code Address. 1cycle Description Maker Code Device Code Must be don’ ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Copy-Back Program Operation CLE ALE RE 00h I Column Page(Row) Address R 8Ah 25 Column Address Address Busy Copy-Back Data Input Command 24 FLASH MEMORY t t PROG WB 10h ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Figure 9. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I & Don t Care) Figure 10. Sequential Row Read1 Operation R/B I 00h Start Add.(4Cycle) 01h & 00h Command) 1st half array Block ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Figure 11. Sequential Row Read2 Operation R/B I/O ~ Start Add.(4Cycle 50h & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16. Figure 15. Multi-Plane Program & ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous Multi-Plane Copy- Back programming of four pages. Partial activation of four planes is also permitted. ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 FLASH MEMORY 32 ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied ...
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... K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Data Protection The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum required before internal circuit gets ready for any command sequences as shown in Figure 25 ...
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Package Dimensions Package Dimensions 48-Pin Lead Plastic Thin Small Out-Line Package Type( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 37 FLASH MEMORY Unit :mm/Inch #48 #25 1.00 0.05 ...