K9K1G08U0M-YIB0 Samsung semiconductor, K9K1G08U0M-YIB0 Datasheet - Page 33

• Manufacturer Part Number: K9K1G08U0M-YIB0
• Description: 128M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

NOTE :
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether
multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The
pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (79h), Reserved(A5h), Multi plane oper-
ation code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence.
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
CLE
CE
WE
ALE
RE
I/O
Figure 22. Read ID Operation 1
I/O No.
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
~
1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
7
2. The pass/fail status applies only to the corresponding plane.
Erase operation, it sets "Fail" flag.
Plane 0 Pass/Fail
Plane 1 Pass/Fail
Plane 2 Pass/Fail
Plane 3 Pass/Fail
Device Operation
Total Pass/Fail
90h
Write Protect
Reserved
Status
Address. 1cycle
00h
Pass : "0"
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Busy : "0"
Protected : "0"
t
CLR
Definition by 70h Command
t
WHR
t
AR1
t
CEA
t
REA
33
Not Protected : "1"
Maker code
Fail : "1"
Ready : "1"
ECh
Device code
79h
Pass : "0"
Pass : "0"
Pass : "0"
Pass : "0"
Pass : "0"
Must be don’t-cared
Busy : "0"
Protected : "0"
Definition by 71h Command
FLASH MEMORY
(1)
(2)
(2)
(2)
(2)
A5h
Not Protected : "1"
Fail : "1"
Ready : "1"
Fail : "1"
Fail : "1"
Fail : "1"
Fail : "1"
Multi-Plane code
C0h