PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 10

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
10
Table 2.
Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 2 of 7)
SDCLK[2:0]
nCS[5]/
GPIO[33]
nCS[4]/
GPIO[80]
nCS[3]/
GPIO[79]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
nCS[0]
RD/nWR
RDY/
GPIO[18]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
nPWE/
GPIO[49]
nPIOW/
GPIO[51]
nPIOR/
GPIO[50]
nPCE[2:1]/
GPIO[53, 52]
Name
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
Type
OCZ
OCZ
SDRAM and/or Synchronous Static Memory clocks. Connect SDCLK[0] to the
clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. SDCLK[1]
and SDCLK[2] should be connected to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the internal memory controller
clock, or the internal memory controller clock divided by 2. At reset, all clock pins
are free running at the divide by 2 clock speed and may be turned off via free
running control register bits in the memory controller. The memory controller also
provides control register bits for clock division and deassertion of each SDCLK
pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static
memory bank 0 is configured for SMROM or SDRAM-timing Synchronous Flash.
SDCLK[2:1] control register assertion bits are always deasserted upon reset.
0 and 2 are not three-stateable, SDCLK1 is three-stateable
Static chip selects. These signals are chip selects for static memory devices such
as ROM and Flash. They are individually programmable in the memory
configuration registers. nCS[5:3] may be used with variable data latency variable
latency I/O devices.
See Note [1]
Static chip select 4.
Static chip select 3.
Static chip select 2.
Static chip select 1.
Static chip select 0. This is the boot memory chip select. nCS[0] is a dedicated
pin.
Read/Write for static interface. Intended for use as a steering signal for buffering
logic
Variable Latency I/O Ready pin (input)
See Note [1]
PCMCIA Output Enable. This PCMCIA signal is an output and performs reads
from memory and attribute space.
See Note [1]
PCMCIA Write Enable. This signal is an output and performs writes to memory
and attribute space.
See Note [1]
PCMCIA I/O Write. This signal is an output and performs write transactions to the
PCMCIA I/O space.
See Note [1]
PCMCIA I/O Read. This signal is an output and performs read transactions from
the PCMCIA I/O space.
See Note [1]
PCMCIA Card Enable. These signals are outputs and select a PCMCIA card. Bit
one enables the high byte lane and bit zero enables the low byte lane.
See Note [1]
Description
Datasheet