PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 19

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

3.1.1.2
Datasheet
Table 3.
Table 4.
PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 3 of 3)
PXA210 Signal Pin Descriptions
Signal definitions for the PXA210 applications processor are described in Table 4. The physical
characteristics of the PXA210 applications processor are shown in Figure 3, “PXA210
Applications Processor” on page 26. The pinout for the PXA210 applications processor is
described in Table 5, “PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order” on
page 27.
Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 1 of 7)
Memory Controller Pins
MA[25:0]
MD[15:0]
nOE
nWE
nSDCS[1:0]
DQM[1:0]
nSDRAS
nSDCAS
SDCKE[0]
Ball #
K14
K15
K16
Pin Name
L1
L2
L3
L4
L5
L6
L7
L8
GPIO[3]
PXTAL
PEXTAL
MA[12]
VSSN
MA[13]
MD[20]
MD[2]
VCC
DQM[3]
MD[28]
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210
OCZ
ICOCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OC
Type
Signal
Memory address bus. (output) Signals the address requested for memory
accesses.
Memory data bus. (input/output) Lower 16 bits of the data bus.
Memory output enable. (output) Connect to the output enables of memory
devices to control data bus drivers.
Memory write enable. (output) Connect to the write enables of memory devices.
SDRAM CS for banks 1 and 0. (output) Connect to the chip select (CS) pins for
SDRAM. For the PXA210 applications processor nSDCS0 can be Hi-Z, nSDCS1
cannot.
SDRAM DQM for data bytes 1 and 0. (output) Connect to the data output mask
enables (DQM) for SDRAM.
SDRAM RAS. (output) Connect to the row address strobe (RAS) pins for all banks
of SDRAM.
SDRAM CAS. (output) Connect to the column address strobe (CAS) pins for all
banks of SDRAM.
SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to
the CKE pins of SMROM and SDRAM-timing Synchronous Flash. The memory
controller provides control register bits for deassertion.
Ball #
N12
N13
N14
N15
N16
N11
P1
P2
P3
P4
P5
VCCN
DREQ[0]/GPIO[20]
VCCN
DREQ[1]/GPIO[19]
GPIO[21]
nPWAIT/GPIO[56]
MA[17]
MA[19]
VCCN
MA[25]
MA[23]
Signal
Signal Descriptions
Ball #
T13
T15
T10
T11
T12
T14
T16
T8
T9
nCS[1]/GPIO[15]
nCS[3]/GPIO[79]
MD[9]
MD[11]
MD[14]
nCS[5]/GPIO[33]
nPWE/GPIO[49]
nPIOR/GPIO[50]
VCCN
Signal
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