PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 38

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
4.6.5
38
Table 15. GPIO Reset Timing Specifications
Figure 7. Sleep Mode Timing
Sleep Mode Timing
Sleep Mode is internally asserted, it and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 7, “Sleep Mode Timing” on page 38 and detailed in Figure 16, “Sleep
Mode Timing Specifications” on page 39 is the required timing parameters for Sleep Mode.
NOTES:
tDHW_OUT_A
tDHW_OUT_F
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check
2. Time is 512*N Processor Clock Cycles plus up to 4 cycles of the 3.6864MHz input clock.
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the
tDHW_OUT
tA_GP[1]
the state of GP[1] before configuring as a Reset to ensure no spurious reset is generated.
assertion of GPIO Reset. The Lock Detector has a maximum time of 350µs plus synchronization.
Symbol
nRESET_OUT
nVDD_FAULT
PWR_EN
Minimum assert time of GP[1]1 in
3.6864MHz input clock cycles
Delay between GP[1] Asserted and
nRESET_OUT Asserted in 3.6864MHz
input clock cycles
Delay between nRESET_OUT asserted
and nRESET_OUT deasserted, Run or
Turbo Mode2
Delay between nRESET_OUT asserted
and nRESET_OUT deasserted, during
Frequency Change Sequence3
GP[x]
VCC
Note: nBA TT_FAULT must be high or Cotulla will not exit Sleep Mode
Note: nBATT_FAULT must be high or the PXA250 applications processor
Description
will not exit Sleep Mode.
t
D_PWR_F
t
D_PWR_R
Min
4
6
5
5
t
A_GP[x]
t
D_F A UL T
Typical
t
DSM_VCC
t
DSM_OUT
Max
380
28
8
-
Datasheet
cycles
cycles
Units
s
s