PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 20

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
20
Table 4.
Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 2 of 7)
SDCKE[1]
SDCLK[0]
SDCLK[1]
nCS[5]/
GPIO[33]
nCS[4]/
GPIO[80]
nCS[3]/
GPIO[79]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
nPWE/
GPIO[49]
nCS[0]
RD/nWR
RDY/
GPIO[18]
L_DD[8]/
GPIO[66]
L_DD[15]/
GPIO[73]
LCD Controller Pins
L_DD(7:0)/
GPIO[65:58]
L_DD[8]/
GPIO[66]
Pin Name
OC
OC
OCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
Type
SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to
the clock enable pins of SDRAM. It is deasserted during sleep. SDCKE[1] is
always deasserted upon reset. The memory controller provides control register bits
for deassertion.
SDRAM and/or Synchronous Static Memory clocks. (output) Connect to the
clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. Connect
SDCLK[1] to the clock pins of SDRAM in bank pairs 0/1. It is driven by either the
internal memory controller clock or the internal memory controller clock divided by
2. At reset, all clock pins are free running at the divide by 2 clock speed and may
be turned off via free running control register bits in the memory controller. The
memory controller also provides control register bits for clock division and
deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to
on if the boot-time static memory bank 0 is configured for SMROM or SDRAM-
timing Synchronous Flash. SDCLK[1] control register assertion bit is always
deasserted on reset. SDCLK[1] can be Hi-Z, SDCLK[0] cannot.
Static chip selects. (output) Chip selects to static memory devices such as ROM
and Flash. Individually programmable in the memory configuration registers.
nCS[5:3] can be used with variable latency I/O devices.
VLIO write enable (output). Used as the write enable signal for Variable Latency
I/O.
Static chip select 0. (output) Chip select for the boot memory. nCS[0] is a
dedicated pin.
Read/Write for static interface. (output) Signals that the current transaction is a
read or write.
Variable Latency I/O Ready pin. (input) Notifies the memory controller when an
external bus device is ready to transfer data.
LCD display data. (output) Transfers pixel information from the LCD Controller to
the external LCD panel.
Memory Controller alternate bus master request. (input) Allows an external
device to request the system bus from the Memory Controller.
LCD display data. (output) Transfers pixel information from the LCD Controller to
the external LCD panel.
Memory Controller grant. (output) Notifies an external device that it has been
granted the system bus.
LCD display data. (outputs) Transfers pixel information from the LCD Controller to
the external LCD panel.
LCD display data. (output) Transfers pixel information from the LCD Controller to
the external LCD panel.
Memory Controller alternate bus master request. (input) Allows an external
device to request the system bus from the Memory Controller.
Signal Descriptions
Datasheet