PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 42

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
4.8
42
Table 20. Synchronous Memory Interface AC Specifications
Peripheral Module AC Specifications
This section describes the AC Specifications for these peripheral units:
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)
Fast Flash (Synchronous READS only)
NOTES:
tsynSDOS
tsynSDOH
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of
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tsynCMD
tsynSDIS
tsynRCD
tsynCLK
tsynCAS
Symbol
tsynDIH
tffCES
tffADV
tffCEH
tffCLK
tffOS
the 99.5 MHz MEMCLK. It can be 99.5MHz at the fastest.
the 132.7 MHz MEMCLK at its fastest.
tffAS
LCD
SSP
SDCLK period
nSDCAS, nSDRAS, nWE, nSDCS assert time
nSDRAS to nSDCAS assert time
nSDCAS to nSDCAS assert time
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)
rise
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output hold time from
SDCLK(2:0) rise
MD(31:0) read data input setup time from SDCLK(2:0) rise
MD(31:0) read data input hold time from SDCLK(2:0) rise
SDCLK period
MA(25:0) setup to nSDCAS (as nADV) asserted
nCS setup to nSDCAS (as nADV) asserted
nSDCAS (as nADV) pulse width
nSDCAS (as nADV) deassertion to nOE assertion
nOE deassertion to nCS deassertion
Description
1
MIN
3.8
3.6
0.5
1.5
0.5
0.5
10
15
1
1
2
1
3
4
MAX
20
20
Datasheet
Units,
Notes
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
ns, 2
ns, 3
ns, 3
ns, 4
ns
ns