PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 44

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PXA250

Manufacturer Part Number
PXA250
Description
Intel-R PXA250 and PXA210 Applications Processors
Manufacturer
INTEL [Intel Corporation]
Datasheet

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PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
4.8.3
44
Figure 9. SSP AC Timing Definitions
Table 22. SSP AC Timing Specifications
Table 23. Boundary Scan Test Signal Timing (Sheet 1 of 2)
Boundary Scan Test Signal Timings
Boundary scan test signal timing is shown in Table 23, “Boundary Scan Test Signal Timing”.
TBSOV1
Symbol
TBSIH1
TBSIH2
TBSCH
TBSCR
TBSIS1
TBSIS2
TBSCL
TBSCF
TOV12
TBSF
TOF1
Symbol
Tsfmv
Trxdh
Tsfmv
Trxds
SFRM_C
SCLK_C
RXD_C
TXD_C
TCK Frequency
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK TDI, TMS
Input Hold from TCK TDI, TMS
Input Setup to TCK nTRST
Input Hold from TCK nTRST
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test) Valid
Delay
SCLK_C rise to SFRM_C driven valid
RXD_C valid to SCLK_C fall (input setup)
hold)
SCLK_C rise to TXD_C valid
SCLK_C fall to RXD_C invalid (input
Parameter
Description
T sfmv
T sfmv
15.0
15.0
25.0
Min
0.0
4.0
6.0
3.0
1.5
1.1
1.5
33.33
Max
5.0
5.0
6.9
5.4
6.9
T rxds
Min
Units
11
MHz
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured at 1.5 V
Measured at 1.5 V
0.8 V to 2.0 V
2.0 V to 0.8 V
Relative to falling edge of TCK
Relative to falling edge of TCK
Relative to falling edge of TCK
T rxdh
Max
21
22
Notes
Units
ns
ns
ns
ns
Datasheet
A4774-01
Notes

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