PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 23

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Table 4.
Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 5 of 7)
AC97 Controller and I
BITCLK/
GPIO[28]
SDATA_IN0/
GPIO[29]
SDATA_IN1/
GPIO[32]
SDATA_OUT/
GPIO[30]
SYNC/
GPIO[31]
nACRESET
I
SCL
SDA
PWM Pins
PWM[1:0]/
GPIO[17:16]
GPIO Pins
GPIO[1:0]
GPIO[57:48]
Crystal and Clock Pins
PXTAL
PEXTAL
TXTAL
TEXTAL
L_DD[12]/
GPIO[70]
L_DD[13]/
GPIO[71]
L_DD[14]/
GPIO[72]
2
C Controller Pins
Pin Name
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OC
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
OA
IA
OA
ICOCZ
ICOCZ
ICOCZ
Type
2
S Controller Pins
AC97 Audio Port bit clock. (input) AC97 clock is generated by Codec 0 and fed
into the PXA210 applications processor and Codec 1.
AC97 Audio Port bit clock. (output) AC97 clock is generated by the PXA210
applications processor.
I
applications processor.
I
processor.
AC97 Audio Port data in. (input) Input line for Codec 0.
I
AC97 Audio Port data in. (input) Input line for Codec 1.
I
AC97 Audio Port data out. (output) Output from the PXA210 to Codecs 0 and 1.
I
AC97 Audio Port sync signal. (output) Frame sync signal for the AC97
Controller.
I
AC97 Audio Port reset signal. (output)
I
I
Pulse Width Modulation channels 0 and 1. (outputs)
General Purpose I/O. Wakeup sources on both rising and falling edges on
nRESET.
General Purpose I/O. Wakeup sources on both rising and falling edges on
nRESET.
3.6864 Mhz crystal input.
3.6864 Mhz crystal output.
32.768 khz crystal input.
32.768 khz crystal output.
LCD display data. (output) Transfers pixel information from the LCD Controller to
the external LCD panel.
RTC clock. (output) Real time clock 1 Hz tick.
LCD display data. (output) Transfers the pixel information from the LCD Controller
to the external LCD panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.
LCD display data. (output) Transfers pixel information from the LCD Controller to
the external LCD panel.
32 kHz clock. (output) Output from the 32 kHz oscillator.
2
2
2
2
2
2
2
2
S bit clock. (input) I
S bit clock. (output) I
S data in. (input) Input line for the I
S system clock. (output) System clock from I
S data out. (output) Output line for the I
S sync. (output) Frame sync signal for the I
C clock. (bidirectional)
C data. (bidirectional).
2
S clock is generated externally and fed into PXA210
2
S clock is generated by the PXA210 applications
Signal Descriptions
2
S Controller.
2
S Controller.
2
S Controller.
2
S Controller.
23