PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 36

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
4.6.2
36
Figure 4. Power-On Reset Timing
Table 13. Power-On Timing Specifications
Note: If Hardware Reset is entered during Sleep Mode, follow the proper power-supply stabilization
times and nRESET timing requirements indicated in Table 13.
Hardware Reset Timing
The timing sequences shown in Hardware Reset Timing for hardware reset assumes stable power
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings
indicated in Section 4.6.1, “Power On Timing” on page 35.
tD_NRESET
tD_NTRST
tR_VCCQ
tD_VCCQ
tR_BATT
tD_JTAG
Symbol
tR_VCC
tD_VCC
tD_OUT
BATT_VCC
JTAG PINS
nRESET
nTRST
VCCQ
VCCN
VCC
BATT_VCC Rise / Stabilization time
VCCQ, VCCN Rise / Stabilization time
VCC, PLL_VCC Rise / Stabilization time
Delay between BATT_VCC at voltage
and before VCCQ and VCCN applied
Delay from VCCQ, VCCN at voltage and
before VCC, PLL_VCC applied
Delay between VCC, PLL_VCC stable
and nTRST deasserted
Delay between nTRST deasserted and
JTAG pins active, with nRESET asserted
Delay between VCC, PLL_VCC stable
and nRESET deasserted
Delay between nRESET deasserted and
nRESET_OUT deasserted
Note: nBA T T_F AULT and nVDD_FAULT must be high before nRESET_OUT is
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is
t
deasserted or the PXA250 applications processor enters Sleep Mode.
deasserted or the Cotulla enters Sleep Mode
R_BA
Description
t
T T
D_VCCQ
t
R_VCCQ
t
D_VCC
t
R_VCC
N
N
t
D_VCC
t
R_VCC
0.01
0.01
0.01
0.03
18.1
Min
50
50
0
0
t
D_NTRST
t
D_NRESET
t
D_JT
Typical
A G
—
t
D_OUT
Max
18.2
100
100
10
Datasheet
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms