HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 118

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Power Down Mode and Wake-up
Rev. 1.10
Entering the IDLE or SLEEP Mode
Standby Current Considerations
Wake-up
There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the
occur:
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps, there are other
considerations which must also be taken into account by the circuit designer if the power consumption
is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance
input pins must be connected to either a fixed high or low level as any floating input pins could create
internal oscillations and result in increased current consumption. This also applies to devices which
have different package types, as there may be unbonbed pins. These must either be setup as outputs or
if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in
which minimum current is drawn or connected only to external circuits that do not draw current, such
as other CMOS inputs. Also note that additional standby current will also be required if the
configuration options have enabled the LIRC oscillator.
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
If the system is woken up by an external reset, the device will experience a full system reset, however,
if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both
of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be
determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or
executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The
TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter
and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to
wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the
instruction following the HALT instruction.
HALT instruction in the application program. When this instruction is executed, the following will
The system clock will be stopped and the application program will stop at the HALT instruction.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
f
system clock.
The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
An external reset
An external falling edge on Port A
A system interrupt
A WDT overflow
SUB
clock source and the WDT is enabled. The WDT will stop if its clock source originates from the
118
February 9, 2011