HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 86

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Note:
Rev. 1.10
1.. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. TnCCLR bit not used
4. No output function -- TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
Capture Input Mode
zero.
TM capture
pin TPn_x
Flag TnAF
Flag TnPF
CCRA Int.
CCRP Int.
TnIO [1:0]
TnPAU
CCRP
TnON
CCRA
To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This
mode enables external signals to capture and store the present value of the internal counter and can
therefore be used for applications such as pulse width measurements. The external signal is supplied
on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the
TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated
using the application program.
When the required edge transition appears on the TPn_0 or TPn_1 pin, the present value in the counter
will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events
occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from
high to low. When a CCRP compare match occurs, the counter will reset back to zero; in this way the
CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs
from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt
signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0
bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or
both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take
place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the
counter will continue to run.
As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the
Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in
this Mode.
Counter Value
Value
Value
YY
XX
Active
edge
00
Rising edge
XX
01
Active
edge
Falling edge
Capture Input Mode
Counter cleared
YY
Active edge
by CCRP
10
XX
Both edges
86
11
Pause
YY
Disable Capture
Resume
TnM [1:0] = 01
Counter
Stop
Counter
Reset
February 9, 2011
Time