HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 41

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The
first is an external hardware reset, which means a low level on the RES pin, the second is using the
Watchdog Timer software clear instructions and the third is via a HALT instruction.
There are two methods of using software instructions to clear the Watchdog Timer, one of which must
be chosen by configuration option. The first option is to use the single ²CLR WDT² instruction while
the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed alternately to successfully clear the Watchdog Timer. Note that
for this second option, if ²CLR WDT1² is used to clear the Watchdog Timer, successive executions of
this instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the
Watchdog Timer. Similarly after the ²CLR WDT2² instruction has been executed, only a successive
²CLR WDT1² instruction can clear the Watchdog Timer.
The maximum time out period is when the 2
LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for
the 2
used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or
IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting
purposes. For systems that operate in noisy environments, using the f
recommended.
15
division ratio, and a minimum timeout of 7.8ms for the 2
Watchdog Timer
41
15
division ratio is selected. As an example, with a 32kHz
8
division ration. If the f
SUB
clock source is strongly
February 9, 2011
SYS
/4 clock is