HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 32

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.10
Bit 7~5
Bit 4
Bit 3
Bit 2
Bit 1
Name
R/W
POR
Control Register
Bit
SMOD Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
CKS2
R/W
CKS2~CKS0: The system clock selection when HLCLK is ²0²
These three bits are used to select which clock is used as the system clock source. In addition to
the system clock source, which is the LIRC, a divided version of the high speed system oscillator
can also be chosen as the system clock source.
FSTEN: Fast Wake-up Control (only for HXT)
This is the Fast Wake-up Control bit which determines if the f
after the device wakes up. When the bit is high, the f
temporary system clock to provide a faster wake up time as the f
LTO: Low speed system oscillator ready flag
This is the low speed system oscillator ready flag which indicates when the low speed system
oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in
the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after
1~2 clock cycles as the LIRC oscillator is used.
HTO: High speed system oscillator ready flag
This is the high speed system oscillator ready flag which indicates when the high speed system
oscillator is stable. This flag is cleared to ²0² by hardware when the device is powered on and
then changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as ²1² by the application program after device power-on. The flag will be low
when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a
high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the
ERC or HIRC oscillator is used.
IDLEN: IDLE Mode control
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE
Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep
the peripheral functions operational as the FSYSON bit is high. If FSYSON bit is low, the CPU
and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP
Mode when a HALT instruction is executed.
7
0
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
0: Disable
1: Enable
0: Not ready
1: Ready
0: Not ready
1: Ready
0: Disable
1: Enable
H
H
H
L
L
H
H
H
/2
/32
/4
/64
/16
/8
(f
(f
LIRC
LIRC
CKS1
R/W
)
)
6
0
CKS0
R/W
5
0
FSTEN
R/W
32
4
0
Enhanced I/O Flash Type MCU
HT68F13/HT68F14/HT68F15
LTO
R
3
0
SUB
clock source can be used as a
SUB
HTO
clock source is initially used
R
SUB
2
0
clock is available.
IDLEN
R/W
1
1
February 9, 2011
HLCLK
R/W
0
1