HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 92
![no-image](/images/no-image-200.jpg)
HT68F14
Manufacturer Part Number
HT68F14
Description
Enhanced I/O Flash Type MCU
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet
1.HT68F14.pdf
(161 pages)
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HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Bit 3
Bit 2
Bit 1~0
Bit 7~0
Bit 7~2
Bit 1~0
Bit 7~0
Name
Name
Name
POR
POR
POR
R/W
R/W
R/W
Bit
Bit
Bit
TM1DL Register
TM1DH Register
TM1AL Register
T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit
Compare Match Output Mode
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control
This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set
high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
T1PWM1~T1PWM0: Select PWM Mode
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0
Unimplemented, read as 0
TM1DH: TM1 Counter High Byte Register bit 1~bit 0
TM1 10-bit Counter bit 9~bit 8
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0
Mode/ Single Pulse Output Mode
R/W
0: Initial low
1: Initial high
0: Active low
1: Active high
0: Non-invert
1: Invert
00: Edge aligned
01: Centre aligned, compare match on count up
10: Centre aligned, compare match on count down
11: Centre aligned, compare match on count up or down
D7
D7
R
7
0
7
7
0
R/W
D6
D6
R
6
0
6
6
0
R/W
D5
D5
R
5
0
5
5
0
92
R/W
D4
D4
R
4
0
4
4
0
R/W
D3
D3
R
3
0
3
3
0
R/W
D2
D2
R
2
0
2
2
0
R/W
D1
D9
D1
R
R
1
0
1
0
1
0
February 9, 2011
R/W
D0
D8
D0
R
R
0
0
0
0
0
0
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