ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 155

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ATMEGA128-16AU SL383

Manufacturer Part Number
ATMEGA128-16AU SL383
Description
Manufacturer
Atmel
Datasheet
Timer/Counter
Timing Diagrams
2467S–AVR–07/09
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 68. Timer/Counter Timing Diagram, no Prescaling
Figure 69
Figure 69. Timer/Counter Timing Diagram, with Prescaler (f
Figure 70
The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF2 in all modes except CTC mode.
/8)
Figure 68
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
MAX
MAX
clk_I/O
BOTTOM
BOTTOM
/8)
T2
) is therefore shown as a
ATmega128
BOTTOM + 1
BOTTOM + 1
155

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