ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 94
ATMEGA128-16AU SL383
Manufacturer Part Number
ATMEGA128-16AU SL383
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA128-16AU_SL383.pdf
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Definitions
Timer/Counter
Clock Sources
Counter Unit
94
ATmega128
tive when no clock source is selected. The output from the clock select logic is referred to as the
timer clock (clk
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC0).
Unit” on page 95.
which can be used to generate an output compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. However, when using the register or bit
defines in a program, the precise form must be used (i.e., TCNT0 for accessing Timer/Counter0
counter value and so on).
The definitions in
Table 51. Definitions
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
chronous Status Register – ASSR” on page
“Timer/Counter Prescaler” on page
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
35
Figure 35. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surrounding environment.
DATA BUS
TCNTn
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The
assignment is dependent on the mode of operation.
T0
).
Table 51
for details. The compare match event will also set the compare flag (OCF0)
direction
are also used extensively throughout the document.
count
clear
bottom
Control Logic
T0
110.
is by default equal to the MCU clock, clk
top
107. For details on clock sources and prescaler, see
TOVn
(Int.Req.)
clk
Tn
Prescaler
Oscillator
See “Output Compare
T/C
I/O
. When the AS0
clk
2467S–AVR–07/09
I/O
TOSC2
TOSC1
“Asyn-
Figure
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