ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 176

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Frame Formats
Parity Bit Calculation
176
ATmega128
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 82
optional.
Figure 82. Frame Formats
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB
and UCSRC. The receiver and transmitter use the same setting. Note that changing the setting
of any of these bits will corrupt all ongoing communication for both the receiver and transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The receiver ignores the
second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first
stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
St
(n)
P
Sp
IDLE
P
P
d
n
odd
even
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must be
high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
illustrates the possible combinations of the frame formats. Bits inside brackets are
St
0
P
P
even
odd
1
=
=
2
d
d
n 1
n 1
–
–
3
⊕
⊕
…
…
4
FRAME
⊕
⊕
[5]
d
d
3
3
⊕
⊕
[6]
d
d
2
2
⊕
⊕
[7]
d
d
1
1
⊕
⊕
[8]
d
d
0
0
⊕
⊕
[P]
0
1
Sp1 [Sp2]
(St / IDLE)
2467S–AVR–07/09