ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 57

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

2467S–AVR–07/09
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 58.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 22. Watchdog Timer Prescale Select
WDP2
0
0
0
0
1
1
1
1
to WDE even though it is set to one before the disable operation starts.
WDP1
0
0
1
1
0
0
1
1
Table
WDP0
See “Timed Sequences for Changing the Configuration of the Watchdog
22.
0
1
0
1
0
1
0
1
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
Typical Time-out
at V
14.8 ms
29.6 ms
59.1 ms
0.12 s
0.24 s
0.47 s
0.95 s
CC
1.9 s
= 3.0V
Typical Time-out
at V
ATmega128
14.0 ms
28.1 ms
56.2 ms
0.11 s
0.22 s
0.45 s
CC
0.9 s
1.8 s
= 5.0V
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