ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 171

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

USART
Dual USART
Overview
2467S–AVR–07/09
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
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The ATmega128 has two USART’s, USART0 and USART1. The functionality for both USART’s
is described below. USART0 and USART1 have different I/O registers as shown in
Summary” on page
neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility
mode, the ATmega128 supports asynchronous operation of USART0 only.
A simplified block diagram of the USART transmitter is shown in
registers and I/O pins are shown in bold.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
362. Note that in ATmega103 compatibility mode, USART1 is not available,
Figure
79. CPU accessible I/O
ATmega128
“Register
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