C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 184
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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C8051F96x
14.3. AES Block Cipher
The basic AES Block Cipher is the basic encryption/decryption algorithm as defined by the NIST standard.
A clock cipher mode is a method of encrypting and decrypting one block of data. The input data and output
data are not manipulated, chained, or exclusive ORed with other data. This simple block cipher mode is
sometimes called the Electronic Code Book (ECB) mode. The Electronic Codebook Mode is illustrated in
Figure 14.3
Each operation represents one block (sixteen bytes) of data. The Plaintext is the plain unencrypted data.
The Ciphertext is the encrypted data. The encryption key and decryption keys are symmetric. The decryp-
tion key is the inverse key of the decryption key. Note that the Encryption operation is not the same as the
decryption operation. The two operations are different and the AES core operates differently depending on
whether encryption or decryption is selected.
Note that each encryption or decryption operation is independent of other operations. Also note that the
same key is used over and over again for each operation.
184
Rev. 0.5
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