C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 337
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C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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SFR Definition 26.2. LCD0CN: LCD0 Control Register
SFR Page = 0x2; SFR Address = 0x9D
Name
Reset
Type
6:5
2:1
Bit
Bit
7
4
3
0
MUXMD[1:0]
CLKDIV[1:0]
Reserved
BLANK
R/W
Name
SIZE
BIAS
7
0
Read = 0. Must Write 0b.
LCD0 Clock Divider.
Divides the SmaRTClock output for use by the LCD0 module. See Table 4.18 on
page 76 for LCD clock frequency range.
00: The LCD clock is the SmaRTClock divided by 1.
01: The LCD clock is the SmaRTClock divided by 2.
10: The LCD clock is the SmaRTClock divded by 4.
11: Reserved.
Blank All Segments.
Blanks all LCD segments using a single bit.
0: All LCD segments are controlled by the LCD0Dn registers.
1: All LCD segments are blank (turned off).
LCD Size Select.
Selects whether 16 or 32 segment pins will be used for the LCD function.
0: P0 and P1 are used as LCD segment pins.
1: P0, P1, P2, and P3 are used as LCD segment pins.
LCD Bias Power Mode.
Selects the mux mode.
00: Static mode selected.
01: 2-mux mode selected.
10: 3-mux mode selected.
11: 4-mux mode selected.
Bias Select .
Selects between 1/2 Bias and 1/3 Bias. This bit is ignored if Static mode is
selected.
0: LCD0 is configured for 1/3 Bias.
1: LCD0 is configured for 1/2 Bias.
R/W
6
0
CLKDIV[1:0]
R/W
5
0
BLANK
Rev. 0.5
R/W
4
0
Function
SIZE
R/W
3
0
2
0
MUXMD[1:0]
R/W
C8051F96x
1
0
BIAS
R/W
0
0
337
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