MPC8306VMAFDCA Freescale Semiconductor, MPC8306VMAFDCA Datasheet
MPC8306VMAFDCA
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MPC8306VMAFDCA Summary of contents
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... To locate published errata or updates for this document, refer to the MPC8306 product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number:MPC8306EC Rev. 2, 09/2011 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...
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... MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev e300c3 Core with Power Management 16-KB 16-KB I-Cache D-Cache FPU DMA Engine 16 KB Multi-User RAM 48 KB Instruction RAM 2 RMII/MII 2x IEEE 1588 Figure 1. MPC8306 Block Diagram ULPI Enhanced Local USB 2.0 HS Bus Controller Host/Device/OTG eSDHC 4 FlexCAN Freescale Semiconductor DDR2 Controller ...
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... Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces. – IEEE Std. 1588™ support – HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8) – HDLC Bus (bit rate Mbps) MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Overview 3 ...
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... Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC slave devices • Integrated programmable interrupt controller (IPIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and internal discrete interrupt sources MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... C interfaces — Two-wire interface — Multiple-master support 2 — Master or slave I C mode support — On-chip digital filtering rejects spikes on the bus 2 — can be used as the boot sequencer MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Overview 5 ...
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... Maintains a one-second count, unique over a period of thousands of years — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock • IEEE Std. 1149.1™ compliant JTAG boundary scan MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. 3. Caution: MV must not exceed GV IN power-on reset and power-down sequences. 4. Caution: OV must not exceed OV IN power-on reset and power-down sequences. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...
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... Temperature); maximum temperature is specified with 20 G/OV DD GND Not to Exceed 10 interface Recommended Unit Value 1.0 V ± 1.0 V ± DD1 DD2 DD3 1.8 V ± 100 mV DD 3.3 V ± 300 105 / Freescale Semiconductor Note C 2 (Junction J ...
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... PORESET. There is no specific power down sequence requirement for the device. I/O voltage supplies (GV with respect to one another. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 3. Output Drive Capability Output Impedance Table 4. Input Capacitance Specification Symbol ...
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... V, ambient temperature, and the core running a Dhrystone process, a junction T DD and 0 SYS_CLK_IN Maximum Unit 0.618 W 0.631 W 0.925 W 0.950 W and AV power. For I/O power 105C, and a smoke test code. J Freescale Semiconductor Note ...
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... Input high voltage Input low voltage SYS_CLK_IN input current SYS_CLK_IN input current SYS_CLK_IN input current MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 6. Typical I/O Power Dissipation Parameter 266 MHz, 1 16 bits 66 MHz, 26 bits TDM serial, HDLC/TRAN serial, ...
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... — KHK SYS_CLK_ IN — — — Min 32 32 512 4 0 Max Unit Note 66.67 MHz 1 41.6 ns — 2 ±150 Max Unit Note — SYS_CLK_IN — SYS_CLK_IN — SYS_CLK_IN — SYS_CLK_IN — Freescale Semiconductor ...
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... Table 12. DDR2 SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 10. PLL Lock Times Min — Symbol Condition –6.0 mA ...
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... CISKEW (typ) = 1.8 V (continued) DD Max Unit — mA — (typ (typ Min Max Unit — 0.5 pF OUT DD (typ) = 1.8 V). DD Max Unit MVREF – 0.25 V — V Min Max Unit ps Freescale Semiconductor Note — — Note 1 1 Note — — Note 1, 2 ...
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... MCK cycle time, (MCK/MCK crossing) ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS output setup with respect to MCK MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor of 1.8V ± 100mV. DD Symbol Min 266 MHz – ...
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... DDR timing (DD) for the time t DDKLDX PowerQUICC II Pro Integrated Communications Processor Family Reference Manual Max Unit ns — 0 — ps — — ns MCK 0 MCK memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH Freescale Semiconductor Note for ...
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... The following figure shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD MDQS[n] MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MCK MCK t MCK t (max) = 0.6 ns DDKHMH t (min) = –0.6 ns DDKHMH Figure 5 ...
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... Min Max Unit 15 — — ns 1.0 — ns — — symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case LBK of the signal in question for 3.3-V DD Freescale Semiconductor Unit A Note for ...
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... LCLK[n] Input Signals: LAD[0:15] Input Signal: LGTA Output Signals: LBCTL/LBCKE/LOE Output Signals: LAD[0:15] LALE MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 50 Figure 7. Local Bus AC Test Load t LBIVKH t LBKHOV t LBKHOZ t ...
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... LUPWAIT Input Signals: LAD[0:15]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...
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... MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers comply with the DC parametric attributes specified in The following table. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH ...
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... MII(M) transmit (TX) clock. For rise and fall times, the latter convention is Min Max 3 3.6 = Min 2. 0 Min GND 0.50 — 2 0.3 DD — –0.3 0.90 — ±5 Min Typical Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII transmit MTKHDX Freescale Semiconductor Unit A Unit for ...
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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 50 Figure 11. AC Test Load ...
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... RMII(RM) reference (X) clock. For rise and fall times, the latter RMX = 50 Figure 14. AC Test Load t MRXR t MRDXKH Min Typical Max — 20 — 35 — — 13 1.0 — 4.0 1.0 — 4.0 symbolizes RMII RMTKHDX Freescale Semiconductor Unit for ...
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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t the latter convention is used with the appropriate letter: R (rise (fall). MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t RMX t ...
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... V ± 300mV Symbol Min f — MDC t — MDC t 32 MDCH t RMXR t RMRDXKH Min Max 3 3.6 = Min 2. 0 Min GND 0.50 2.00 — — 0.80 — ±5 Typical Max Unit 2.5 — MHz 400 — ns — — ns Freescale Semiconductor Unit A Note — — — ...
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... R (rise (fall). The following figure shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 17. MII Management Interface Timing Diagram MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor is 3.3 V ± 300mV Symbol Min t 10 MDKHDX t 8 ...
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... DD Typ Max Unit 9 — RX_CLK 50 60 — 250 ps — 2.0 ns — 2.0 ns — — — 3.0 ns — — but also defined by the recovered clock. For Freescale Semiconductor unit μA Note — — — — — % — — 2 ...
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... The following table provides the DC electrical characteristics for the MPC8306 TDM/SI. Table 28. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t T1588CLKOUT t T1588CLKOUTH t T1588OV T1588CLKOUT Figure 18. IEEE 1588 Output AC Timing ...
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... Figure 20. TDM/SI AC Test Load Table 29. Note that although the specifications t SEIXKH t SEKHOV t SEKHOX 1 2 Symbol Min Max SEKHOV SEKHOX t 5 — SEIVKH t 2 — SEIXKH symbolizes the TDM/SI SEKHOX Freescale Semiconductor Unit for ...
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... The following figure provides the AC test load. Output MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 30. HDLC DC Electrical Characteristics Symbol Condition – ...
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... The following table provides the DC electrical characteristics for the USB interface. 11.1.2 USB AC Electrical Specifications The following table describes the general timing parameters of the USB interface. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 31. Note that although the specifications t HEIXKH t HEKHOV t HEKHOX t HIIXKH t HIIVKH t HIKHOV t HIKHOX Freescale Semiconductor ...
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... The following figures provide the AC test load and signals for the USB, respectively. Output USBDR_CLK Input Signals t Output Signals MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 32. USB DC Electrical Characteristics Symbol ...
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... Table 35. DUART AC Timing Specifications Value 256 >1,000,000 16 th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Min Max Unit 0.3 DD –0.3 0.8 OV – 0.2 — DD — 0.2 — ±5 Table 1 and Table 2. Unit Note baud — baud 1 — 2 Freescale Semiconductor A ...
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... SD_CLK clock low time—Full-speed/High-speed mode SD_CLK clock high time—Full-speed/High-speed mode SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 3 Symbol Condition V — ...
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... BUS HOST CARD SHSCK VM = Midpoint Voltage ( SHSIVKH t SHSKHOV VM = Midpoint Voltage (OV DD Min Max Unit 2.5 — ns – for outputs. For example, t FHSKHOV t t SHSCKL SHSCKH t t SHSCKF SHSCKR / SHSIXKH /2) Freescale Semiconductor Notes ...
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... It is referenced in IN 14.2 FlexCAN AC Timing Specifications The following table provides the AC timing specifications for the FlexCAN interface. For recommended operating conditions, see Parameter Min Baud rate MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 2 Symbol – ...
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... C interface of the MPC8306. 1 Min Max f 0 400 I2C t 1.3 — I2CL t 0.6 — I2CH 0.6 — t I2SVKH t 0.6 — I2SXKL t 100 — I2DVKH 3 t 300 0.9 I2DXKL 0.1 C 300 I2CR B Freescale Semiconductor Notes V — V — — 4 Unit kHz s s s s ns s ns ...
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... The following figure shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Electrical Specifications (continued) Table 40). Symbol t (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example symbolizes I C timing (I2) for the time that the data with respect to the start condition clock reference (K) going to the low (L) state or hold time ...
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... V Figure 31. Timers AC Test Load Min Max 2.4 — — 0.5 — 0.4 2 0.3 DD –0.3 0.8 OV — ± Symbol Min t 20 TIWID ns to ensure proper operation. TIWID Freescale Semiconductor Unit A Unit ns ...
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... GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least t The following figure provides the AC test load for the GPIO. Output MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 44. GPIO DC Electrical Characteristics Symbol Condition – ...
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... 6 3 not relevant for those pins. OH PIWID 1,2 Min Max 2 0.3 DD –0.3 0.8 — ±5 2.4 — — 0.5 — 0 Symbol Min t 20 PIWID ns to ensure proper operation when working Freescale Semiconductor Unit V V Unit ns ...
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... AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 48. SPI DC Electrical Characteristics Symbol Condition ...
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... Output high voltage Output low voltage Output low voltage MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev NEIXKH t NEKHOV t NIIXKH t NIIVKH t NIKHOV Symbol Condition – Min Max Unit 2.4 — V — 0.5 V — 0.4 V Freescale Semiconductor ...
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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: Valid times: MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Condition V — — ...
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... VM = Midpoint Voltage (OV DD /2) Figure 38. TRST Timing Diagram 1 (continued) Min Max Unit ns 2 — 2 — the midpoint of the signal in question. TCLK Figure symbolizes JTAG device JTDVKH clock reference (K) JTG JTGR t JTGF VM Freescale Semiconductor Notes 36). for ...
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... The following figure provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 39. Boundary-Scan Timing Diagram ...
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... The following figure shows the mechanical dimensions and bottom surface nomenclature of the MPC8306, 369-MAPBGA package. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev and Section 21.2, “Mechanical Dimensions of the MPC8306 MAPBGA,” 19 mm MAPBGA 369 0.80 mm 1.48 mm; Min = 1.31mm and Max 1.61mm 3 0.5 Cu (VM package) 0.40 mm Section 21.1, “Package Freescale Semiconductor ...
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... Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Package and Pin Listings MPC8306 MAPBGA ...
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... Freescale Semiconductor — — — — — — — — — — — — — — — — — — — — — — — — — — ...
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... LAD[2] LAD[3] LAD[4] LAD[5] LAD[6] LAD[7] LAD[8] LAD[9] LAD[10] LAD[11] LAD[12] LAD[13] LAD[14] LAD[15] LA[16] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type ...
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... — — — — — — — — — — — — — — — DD Freescale Semiconductor ...
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... USBDR_TXDRXD[2]/UART1_SOUT[2]/ UART1_RTS_B1/QE_BRG[1] USBDR_TXDRXD[3]/UART1_SIN[2]/ UART1_CTS_B1/QE_BRG[2] USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3] USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4] USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type Clock Interface P23 R23 V23 ...
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... — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...
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... FEC3_COL/GPIO[48] FEC3_CRS/GPIO[49] FEC3_RX_CLK/GPIO[50] FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO[51] FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO[52] FEC3_RXD0/FEC2_TMR_TX_ESFD/GPIO[53] FEC3_RXD1/FEC2_TMR_RX_ESFD/GPIO[54] FEC3_RXD2/TSEC_TMR_TRIG1/GPIO[55] FEC3_RXD3/TSEC_TMR_TRIG2/GPIO[56] FEC3_TX_CLK/TSEC_TMR_CLK/GPIO[57] FEC3_TX_EN/TSEC_TMR_GCLK/GPIO[58] FEC3_TX_ER/TSEC_TMR_PP1/GPIO[59] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type AC17 AB16 AC16 AC15 AB14 FEC2/GPIO AC14 AB13 ...
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... IO OV — — — — — — — — — — — — DD — — — — — — — — — — — — — — — Freescale Semiconductor ...
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... This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin This pin has weak pull-up that is always enabled. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number ...
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... Core PLL to DDR csb_clk memory controller ddr_clk Clock Unit lbc_clk System PLL to local bus csb_clk to rest of the device qe_clk CLK Gen core_clk DDR MEMC_MCK Clock Divider MEMC_MCK /2 /n LBC Clock LCLK[0:1] Divider QE Block Freescale Semiconductor DDR Memory Device Local Bus Memory Device ...
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... The LBC clock divider ratio is controlled by LCRR[CLKDIV]. For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor csb_clk = SYS_CLK_IN × SPMF CEPDF) Clocking Eqn ...
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... Table 53. Configurable Clock Units Default Frequency csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 NOTE Table 2). 1 Max Operating Frequency 2 NOTE the LBCM, DDRCM, and SPMF parameters in the reset Options Unit 266 MHz 133 MHz 233 MHz 167 MHz 66 MHz Table 55 shows the multiplication factor Freescale Semiconductor ...
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... RCWL[COREPLL] 0-1 2-5 nn 0000 00 0001 01 0001 10 0001 11 0001 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 55. System PLL Multiplication Factors System PLL Multiplication Factor Table 56. CSB Frequency Options 25 2:1 3:1 4:1 5:1 125 6:1 Table 57. e300 Core PLL Configuration core_clk : csb_clk Ratio 6 n ...
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... NOTE QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ VCO Divider 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 RCWL[CEPDF) Reserved 2 3 4 5 6 Freescale Semiconductor ...
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... PLLs is configured separately. The following table shows suggested PLL configurations for 33 and 66 MHz input clocks. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ Table 59. QUICC Engine PLL VCO Divider ...
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... Table 60. Suggested PLL Configurations Input Clock CEPMF CEDF Frequency (MHz) 0111 0 33.33 0111 1 66.67 0111 0 33.33 1001 0 25 0111 1 66.67 QUICC CSB Core Engine Frequency Frequency Frequency (MHz) (MHz) (MHz) 133.33 266.66 233 133.33 266.66 233 133.33 333.33 233 125 312.5 225 133.33 333.33 233 Freescale Semiconductor ...
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... Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, T where junction temperature (C) J MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Board type Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — — ...
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... J MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev can be used to determine the junction temperature with a JT – are possible Eqn. 2 Eqn. 3 Freescale Semiconductor ...
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... Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor ...
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... SYS_CLK_IN ) Section 22.2, “System PLL Configuration.” generates the core clock as a slave to the system clock. The frequency ) DD3 Section 22.3, “Core PLL Configuration.” which uses the same reference as the system PLL. The QUICC ) DD1 Eqn. 5 Freescale Semiconductor ...
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... These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor , and preferably these voltages are derived DD ...
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... source source )) 1/R . Solving for the output impedance gives 1 2 source source 2 C). /2 (see Figure DD and R are designed to be close to each SW2 SW1 P OGND . Second, the output voltage is measured term = source Freescale Semiconductor DD 45). The . The ...
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... DDR memory speed and QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask revision number. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor , 105C. Table 62. Impedance Characteristics 42 Target ...
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... MMMMM is the mask number. YWWLAZ is the assembly traceability code. Table 64. SVR Settings Package SVR (Rev 1.0) MAPBGA 0x8110_0210 D C QUICC DDR2 Revision Engine Frequency Frequency D = 266 MHz C = 233 MHz Contact local F = 333 MHz Freescale sales office SVR (Rev 1.1) 0x8110_0211 Freescale Semiconductor A Level ...
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... In Part Nomenclature field for QUICC Engine frequency, C now denotes 233 MHz. Updated • Added SPISEL_BOOT in MPC8306 Pin out Listing • Corrected SPISEL Pin Type in 0 03/2011 Initial Release MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 65. Document Revision History Substantive Change(s) Table 63. Table 5. ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...