MPC8306VMAFDCA Freescale Semiconductor, MPC8306VMAFDCA Datasheet - Page 62

• Manufacturer Part Number: MPC8306VMAFDCA
• Description: Microprocessors - MPU E300 MP 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8306VMAFDCA

• Rohs: yes
• Processor Series: PowerQUICC II Pro
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 233 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB, 48 KB
• Interface Type: CAN, Ethernet, I2C, SPI, UART, USB
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA
• I/o Voltage: 1.8 V
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 56
• Number Of Timers: 8

Clocking
22.4
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The
following table shows the multiplication factor encodings for the QUICC Engine PLL.
62
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
RCWL[CEPMF]
00000–00001
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
0-1
00010
00011
00100
00101
00110
QUICC Engine PLL Configuration
RCWL[COREPLL]
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
Core VCO frequency = core frequency  VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
2-5
RCWL[CEPDF]
Table 58. QUICC Engine PLL Multiplication Factors
Table 57. e300 Core PLL Configuration (continued)
0
0
0
0
0
0
6
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
core_clk : csb_clk Ratio
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
NOTE
1.5:1
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(1 + RCWL[CEPDF)
Reserved
 2
 3
 4
 5
 6
VCO Divider
Freescale Semiconductor
 2
 4
 8
 8
 2
 4
 8
 8
 2
 4
 8
 8
 2
 4
 8
 8