MPC8306VMAFDCA Freescale Semiconductor, MPC8306VMAFDCA Datasheet - Page 61

• Manufacturer Part Number: MPC8306VMAFDCA
• Description: Microprocessors - MPU E300 MP 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8306VMAFDCA

• Rohs: yes
• Processor Series: PowerQUICC II Pro
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 233 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB, 48 KB
• Interface Type: CAN, Ethernet, I2C, SPI, UART, USB
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA
• I/o Voltage: 1.8 V
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 56
• Number Of Timers: 8

coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB
frequency for selected csb_clk to SYS_CLK_IN ratios.
22.3
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Freescale Semiconductor
00
01
10
11
nn
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
0-1
Core PLL Configuration
RCWL[COREPLL]
SPMF
0010
0100
0101
0011
0110
0000
0001
0001
0001
0001
2-5
RCWL[SPMF]
0111–1111
csb_clk : sys_clk_in Ratio
0000
0001
0010
0100
0101
0011
0110
Table 55. System PLL Multiplication Factors
6
n
0
0
0
0
Table 57. e300 Core PLL Configuration
2:1
3:1
4:1
5:1
6:1
Table 56. CSB Frequency Options
(PLL off, csb_clk clocks core directly)
core_clk : csb_clk Ratio
PLL bypassed
1:1
1:1
1:1
1:1
125
25
System PLL Multiplication Factor
csb_clk Frequency (MHz)
SYS_CLK_IN(MHz)
Reserved
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
33.33
133
167
(PLL off, csb_clk clocks core directly)
PLL bypassed
VCO Divider
66.67
133
2
4
8
8
Clocking
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