MPC8306VMAFDCA Freescale Semiconductor, MPC8306VMAFDCA Datasheet - Page 63

• Manufacturer Part Number: MPC8306VMAFDCA
• Description: Microprocessors - MPU E300 MP 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8306VMAFDCA

• Rohs: yes
• Processor Series: PowerQUICC II Pro
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 233 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB, 48 KB
• Interface Type: CAN, Ethernet, I2C, SPI, UART, USB
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA
• I/o Voltage: 1.8 V
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 56
• Number Of Timers: 8

The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in the
following table.
22.5
To simplify the PLL configurations, the MPC8306 might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs is configured separately.
The following table shows suggested PLL configurations for 33 and 66 MHz input clocks.
Freescale Semiconductor
RCWL[CEPMF]
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
01001–11111
01000
00111
Suggested PLL Configurations
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF)  (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
RCWL[CEVCOD]
Table 58. QUICC Engine PLL Multiplication Factors (continued)
RCWL[CEPDF]
00
01
10
11
0
0
0
Table 59. QUICC Engine PLL VCO Divider
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
NOTE
(1 + RCWL[CEPDF)
Reserved
 7
 8
VCO Divider
Reserved
2
4
8
Clocking
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