MPC8306VMAFDCA Freescale Semiconductor, MPC8306VMAFDCA Datasheet - Page 12

• Manufacturer Part Number: MPC8306VMAFDCA
• Description: Microprocessors - MPU E300 MP 333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8306VMAFDCA

• Rohs: yes
• Processor Series: PowerQUICC II Pro
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 233 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB, 48 KB
• Interface Type: CAN, Ethernet, I2C, SPI, UART, USB
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA
• I/o Voltage: 1.8 V
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 56
• Number Of Timers: 8

RESET Initialization
4.2
The primary clock source for the MPC8306 is SYS_CLK_IN. The following table provides the clock input
(SYS_CLK_IN) AC timing specifications for the MPC8306. These specifications are also applicable for
QE_CLK_IN.
5
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8306. The following table provides the reset initialization AC timing specifications for the reset
component(s).
12
SYS_CLK_IN frequency
SYS_CLK_IN cycle time
SYS_CLK_IN rise and fall time
SYS_CLK_IN duty cycle
SYS_CLK_IN jitter
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).
Required assertion time of HRESET to activate reset flow
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN
HRESET assertion (output)
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
Input hold time for POR config signals with respect to negation of
HRESET
Notes:
1. t
2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].
frequencies.
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
II Pro Integrated Communications Processor Family Reference Manual.
SYS_CLK_IN
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
RESET Initialization
AC Electrical Characteristics
Parameter/Condition
is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306 PowerQUICC
Parameter/Condition
Table 9. RESET Initialization Timing Specifications
Table 8. SYS_CLK_IN AC Timing Specifications
t
KHK
f
t
SYS_CLK_IN
SYS_CLK_IN
Symbol
t
KH
/t
SYS_CLK_
—
IN
, t
KL
Min
1.1
24
15
40
—
Min
512
32
32
4
0
Typical
—
—
—
—
—
Max
—
—
—
—
—
66.67
±150
Max
41.6
2.8
60
Freescale Semiconductor
t
t
t
t
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
Unit
ns
Unit
MHz
ns
ns
ps
%
Note
Note
1, 2
4, 5
1, 2
—
1
2
3
1
1
1