LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 11

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-5. Delay Locked Loop Diagram (DLL)
Table 2-5. DLL Signals
CLKI
CLKFB
RSTN
ALUHOLD
UDDCNTL
DCNTL[8:0]
CLKOP
CLKOS
LOCK
SMIADDR[9:0]
SMICLK
SMIRSTN
SMIRD
SMIWDATA
SMIWR
SMIRDATA
internal), from clock net
(CLKOP) or from a user
SMI
ALUHOLD
UDDCNTL
clock (pin or logic)
from CLKOP (DLL
or external pin)
(from routing
CLKFB
RSTN
CLKI
Signal
15
÷4
÷2
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Clock input from external pin or routing
DLL feed input from DLL output, clock net, routing or external pin
Active low synchronous reset
Active high freezes the ALU
Synchronous enable signal (hold high for two cycles) from routing
Active high phase lock indicator
SMI Clock
SMI Read
SMI Write
Encoded digital control signals for PIC INDEL and slave delay calibration
The primary clock output
The secondary clock output with fine phase shift and/or division by 2 or by 4
SMI Address
SMI Reset (Active low)
SMI Write Data
SMI Read Data
Reference
Feedback
Frequency
Detector
Phase
Arithmetic
Logic Unit
2-8
Description
Delay Chain
Delay0
Delay1
Delay2
Delay3
Delay4
LatticeECP2 Family Data Sheet
Detect
Lock
Output
Muxes
Control
Output
Digital
Cycle
Cycle
Duty
Duty
50%
50%
Architecture
÷4
÷2
9
CLKOP
CLKOS
LOCK
DCNT
SMIRD