LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 62

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
LatticeECP2 External Switching Characteristics
General I/O Pin Parameters (Using Primary Clock without PLL)
t
t
t
t
t
f
General I/O Pin Parameters (Using Primary Clock with PLL)
t
t
t
t
t
DDR
t
t
t
t
f
f
SPI4.2 I/O Pin Parameters
t
t
t
t
SFI4 I/O Pin Parameters
t
t
t
t
XGMII I/O Pin Parameters
t
t
CO
SU
H
SU_DEL
H_DEL
MAX_IO
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
MAX_DDR2
DVACLKSPI
DVECLKSPI
DIASPI
DIBSPI
DVACLKSFI
DVECLKSFI
DIASFI
DIBSFI
SUXGMII
HXGMII
Parameter
2
and DDR2
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
DDR Clock Frequency
Data Valid After CLK
Data Hold After CLK
Data Invalid After Clock
Data Invalid Before Clock
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Invalid After Clock
Data Invalid Before Clock
Data Setup Before Read Clock
Data Hold After Read Clock
3
I/O Pin Parameters
4
5
Description
4
Over Recommended Operating Conditions
6
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
Device
3-15
1
1
Min.
0.24
0.02
—
—
—
—
—
—
—
—
—
—
—
—
-7
Max.
3.49
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
Min.
0.15
0.11
—
—
—
—
—
—
—
—
—
—
—
—
-6
Max.
3.79
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0.09
0.23
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
4.10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
UI
UI
UI
UI
ps
ps
ps
ps
ps
ps
ps
ps