LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 66

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
LatticeECP2 Internal Switching Characteristics
t
t
t
t
t
Dynamic Delay on Each PIO
t
GPLL Parameters
t
t
SPLL Parameters
t
t
DSP Block Timing
t
t
t
t
t
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t
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t
t
1. Internal parameters are characterized but not tested on every device.
2. These parameters include the Adder Subtractor block in the path.
Timing v.
SUCE_EBR
HCE_EBR
RSTO_EBR
SUBE_EBR
HBE_EBR
DEL_ADJ_RNG
RSTREC_GPLL
RSTSU_GPLL
RSTREC_SPLL
RSTSU_SPLL
SUI_DSP
HI_DSP
SUP_DSP
HP_DSP
SUO_DSP
HO_DSP
COI_DSP
COP_DSP
COO_DSP
SUADSUB
HADSUB
Parameter
2
2
2
Clock Enable Setup Time to EBR Output
Register (Read Clk)
Clock Enable Hold Time to EBR Output
Register (Read Clk)
Reset To Output Delay Time from EBR
Output Register (Asynchronous)
Byte Enable Set-Up Time to EBR Output
Register
Byte Enable Hold Time to EBR Output
Register
Delay Adjustment Range (in Nine Delay
Steps)
Input Register Setup Time
Input Register Hold Time
Pipeline Register Setup Time
Pipeline Register Hold Time
Output Register Setup Time
Output Register Hold Time
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
AdSub Input Register Setup Time
AdSub Input Register Hold Time
Description
Over Recommended Operating Conditions
3-19
Min.
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-7
Max.
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—
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—
—
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—
—
—
—
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1
DC and Switching Characteristics
(Continued)
LatticeECP2 Family Data Sheet
Min.
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—
—
-6
Max.
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—
—
—
—
—
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—
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—
Min.
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—
—
—
—
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-5
Max.
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—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns