LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 40

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Architecture
Lattice Semiconductor
LatticeECP2 Family Data Sheet
DQSXFER
LatticeECP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
o
that require DQS strobe be shifted 90
. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeECP2 devices have nine sysIO buffer banks: eight banks for user I/Os arranged two per side. The ninth
sysIO buffer bank (Bank 8) is located adjacent to Bank 3 and has dedicated/shared I/Os for configuration. When a
shared pin is not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O
standards. Each sysIO bank has its own I/O supply voltage (V
). In addition, each bank, except Bank 8, has
CCIO
voltage references, V
and V
, that allow it to be completely independent from the others. Bank 8 shares two
REF1
REF2
voltage references, V
and V
, with Bank 3. Figure 2-34 shows the nine banks and their associated sup-
REF1
REF2
plies.
In LatticeECP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V
. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
CCIO
pendent of V
.
CCIO
Each bank can support up to two separate V
voltages, V
and V
, that set the threshold for the refer-
REF
REF1
REF2
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
2-37