LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 4

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

LatticeECP2 Family Data Sheet
Architecture
February 2006
Advance Data Sheet
Architecture Overview
Each LatticeECP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-
DSP™ Digital Signal Processing blocks as shown in Figure 2-1.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit
without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF
block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for
flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-
dimensional array. Only one type of block is used per row.
The LatticeECP2 family of devices contain up to two rows of sysMEM EBR blocks. sysMEM EBRs are large dedi-
cated 18K fast memory blocks. Each sysMEM block can be configured in variety of depths and widths of RAM or
ROM. In addition, LatticeECP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the
LatticeECP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of
the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support
to aid in the implementation of the high speed source synchronous standards such as SPI4.2 along with memory
interfaces including DDR2.
Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2 architecture provides two
General PLLs (GPLL) and up to four Standard PLLs (SPLL) per device. In addition, each LatticeECP2 family mem-
ber provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom-most
EBR row; the DLL block located towards the edge of the device. The SPLL blocks are located at the end of the
other EBR/DSP rows.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located toward the center of this EBR row. Every device in the LatticeECP2 family sup-
ports a sysCONFIG™ port located in the corner between banks four and five, which allows for serial or parallel
device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The LatticeECP2 devices use 1.2V as their core voltage.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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