LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 29

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the ispLEVER IPexpress tool which provides the option to configure
each DSP module (or group of modules) or by direct HDL instantiation. In addition, Lattice has partnered with The
MathWorks
ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2 DSP
include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/
Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest
list of available DSP IP cores.
Resources Available in the LatticeECP2 Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP2 family. Table 2-10 shows
the maximum available EBR RAM Blocks in each LatticeECP2 device. EBR blocks, together with Distributed RAM
can be used to store variables locally for fast DSP operations.
Table 2-9. Maximum Number of DSP Blocks in the LatticeECP2 Family
Table 2-10. Embedded SRAM in the LatticeECP2 Family
LatticeECP2 DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2 family.
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
®
to support instantiation in the Simulink
DSP Block
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
18
22
3
6
7
8
EBR SRAM Block
9x9 Multiplier
®
tool, a graphical simulation environment. Simulink works with
2-26
144
176
24
48
56
64
12
15
18
21
56
3
Total EBR SRAM
18x18 Multiplier
LatticeECP2 Family Data Sheet
(Kbits)
1032
221
277
332
387
12
24
28
32
72
88
55
36x36 Multiplier
Architecture
18
22
3
6
7
8